5.0V and 3.3V PCI interfacing with Altera Cyclone III

Started by wallge in comp.arch.fpga12 years ago 6 replies

I am working on building a PC/104+ board with support for a 32 bit master target PCI interface. I want to be able to support the 32-bit 33MHz...

I am working on building a PC/104+ board with support for a 32 bit master target PCI interface. I want to be able to support the 32-bit 33MHz PCI bus at both 3.3V and 5.0V. I want to use the Altera PCI master/target IP core to support the PCI interface and connect it to my SOPC builder system through the Avalon memory mapped interface. I have read through Altera App Note 330, which talks ab...


Altera Flex10K support ?

Started by Nicolas Matringe in comp.arch.fpga10 years ago 5 replies

Hi I have found old parts lying around in the lab and I could put them to good use. Alas, they are not supported by Quartus any more. Do you...

Hi I have found old parts lying around in the lab and I could put them to good use. Alas, they are not supported by Quartus any more. Do you know which version of the tool I should get (and where I could get it, if Altera doesn't provide it) ? Thanks Nicolas


Ethernet on Altera FPGA: Help required

Started by renupriya in comp.arch.fpga12 years ago 1 reply

Hi ... I'm very new to working with altera and quartus.I'm working with NiOS II development board(Cyclone III EP3C25). I have to create a design...

Hi ... I'm very new to working with altera and quartus.I'm working with NiOS II development board(Cyclone III EP3C25). I have to create a design which has a NiOS processor, SRAM, Ethernet MAC and Ethernet Management Interface and other components.But the MAC and MI are custom components and not altera's IPs. I need to know how to instantiate these components in SOPC builder and I'm not aware ...


Program Xilinx with Altera JTAG Programmer?

Started by jackm in comp.arch.fpga7 years ago 13 replies

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship...

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship from China and are fake copies I assume, they cost less than $7 inc shipping. If I download and install Altera Quartus II software can I use that to JTAG program my device file compiled in Xilinx ISE? Thanks for any help.


About Altera FPGA Board

Started by Anonymous in comp.arch.fpga16 years ago 10 replies

There are three sets of holes for accessing signal I/O pins on the altera fpga board ...they are flex_expan_A,B and C on the Altera FPGA board....

There are three sets of holes for accessing signal I/O pins on the altera fpga board ...they are flex_expan_A,B and C on the Altera FPGA board. I don't understand the table that shows all the hole number and the signal/pin connection in flex_expan_A, can anyone explain about that? Thank you very much!! Laura


About Altera patent application "Logic Cell Supporting Addition of Three Binary Words"

Started by Weng Tianxiang in comp.arch.fpga12 years ago 21 replies

Hi, I recently read Altera Stratix II, III and IV device handbook and found its 3-bit addition circuit is really a genius invention. But I was...

Hi, I recently read Altera Stratix II, III and IV device handbook and found its 3-bit addition circuit is really a genius invention. But I was surprised to find that Altera patent application "Logic Cell Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has not been approved to be a patent so far today, even though many Altera later patent applications based on the invention ...


Does Altera has some analogous file like XDL of Xilinx?

Started by in comp.arch.fpga14 years ago 3 replies

Hi: Does anyone know whether Altera has some analogous file like XDL of Xilinx so that we can read the place and route of the circuit...

Hi: Does anyone know whether Altera has some analogous file like XDL of Xilinx so that we can read the place and route of the circuit of Altera's FPGA textually? If not, I wonder whether there is a third tool that can generate an intermediate file so that it can accomplish this process: Altera FPGA circuit (Placed and Routed) intermediate file Xilinx FPGA circuit (Placed and Ro


Design tools comparison between Xilinx, Altera and Lattice for FPGA designs

Started by Luc in comp.arch.fpga16 years ago 7 replies

Guys, I'm trying to compare Altera, Xilinx and Lattice tools (free version) Can Xilinx, Altera and Lattice supporters comment? I...

Guys, I'm trying to compare Altera, Xilinx and Lattice tools (free version) Can Xilinx, Altera and Lattice supporters comment? I found: Lattice starter has included Leonardo/Precision RTL and Synplify, no ModelSim Xilinx ISE WebPack : XST, no Leonardo/Precision, no Synplify, no ModelSim Altera QuartusII Web Edition: support for Synplify, Precision and Modelsim? I know it's a simple c...


Altera's altsyncram MAXIMUM_DEPTH

Started by Peter Sommerfeld in comp.arch.fpga18 years ago 11 replies

What does this generic means? I am wondering if I am missing out on a possible memory optimization. Altera's docs are decidedly vague and a...

What does this generic means? I am wondering if I am missing out on a possible memory optimization. Altera's docs are decidedly vague and a search on their website brings up nothing. -- Pete


Altera Quartus II 8.1

Started by Leon in comp.arch.fpga13 years ago 2 replies

I've just downloaded the latest Altera Web Edition software. I was pleased to see that they have removed the requirement for a license that has...

I've just downloaded the latest Altera Web Edition software. I was pleased to see that they have removed the requirement for a license that has to be renewed every six months. NIOS II is provided free, also. Leon


ALTERA EPXA1 SDRAM BUG

Started by Ralf in comp.arch.fpga16 years ago

Hi all, have everyone experience about a second SDRAM with the Altera FPGA+HARCORE-CPU EPXA1? Its is unpossible for me to access the second...

Hi all, have everyone experience about a second SDRAM with the Altera FPGA+HARCORE-CPU EPXA1? Its is unpossible for me to access the second SDRAM. I used a modified "Hello World" program from ALTERA, Linux running on the hardcore CPU and ARMBOOT to address the second SDRAM (Chip-Select SD-CS1) device. But I always get the content of the first SDRAM (Chip-Select SD-CS0). Both SDRAM devices...


Quartus II 7.2 web edition - Linux or not?

Started by H. Peter Anvin in comp.arch.fpga14 years ago 12 replies

I just got an email from Altera, saying: ear Altera Customer, The new Quartus® II Web Edition Software version 7.2 is now available for...

I just got an email from Altera, saying: ear Altera Customer, The new Quartus® II Web Edition Software version 7.2 is now available for download. New features include: [...blah...] * Get complete OS support for Linux in addition to 64-bit Windows Vista However, on the download page they still have: For Solaris or Linux support, purchase an Altera software subscrip...


High Speed Development Board

Started by freechip in comp.arch.fpga16 years ago 1 reply

Hi, I am working on a 10 Gigabit Ethernet Projet. I have to choose a High-Speed Development Board. I don't know yet which kind of FPGA I am...

Hi, I am working on a 10 Gigabit Ethernet Projet. I have to choose a High-Speed Development Board. I don't know yet which kind of FPGA I am going to use. (Altera or Xilinx). I saw on Altera's Web Site the "Stratix GX High-Speed Development Board" http://www.altera.com/literature/ug/ug_stx_gx_hs_dev_kit.pdf I saw on Altera's Web Site a second High Speed Development: "Stratix II High-Spee...


Migration Altera APEX20KE to ???

Started by Manfred Balik in comp.arch.fpga16 years ago 4 replies

In my actual design I'm using an Altera APEX20KE with 200,000 gates. In my next (larger) design I want to use an newer and maybe cheaper FPGA. I...

In my actual design I'm using an Altera APEX20KE with 200,000 gates. In my next (larger) design I want to use an newer and maybe cheaper FPGA. I don't want to change to an other vendor, I intend to use an Altera FPGA. Which one shall I use??? My first choice was a CYCLONE, which is much cheaper, but is this familie powerful enough compared to an APEX20KE??? My second choice was a STRATIX, w...


Problem for DAC/ADC conversion (Stratix EP1S25 Development Board)

Started by A. Abellard in comp.arch.fpga17 years ago

(2nd version of the message... more correct English this time) Hello, I would like to request some help for some students that work on...

(2nd version of the message... more correct English this time) Hello, I would like to request some help for some students that work on an Altera Stratix EP1S25 development board http://www.altera.com/products/devkits/altera/kit-dsp_stratix.html They try to deal with the Digital Analog Conversion , so they wrote programs on VHDL where they declare a bit vector with a certain value, and s...


Altera Cyclone II DQ/DQS pins location

Started by Anonymous in comp.arch.fpga15 years ago 4 replies

Hello group, I have an issue with porting my high-speed DDR interface to Altera Cyclone II device. As far as datasheet says, Altera Cyclone II...

Hello group, I have an issue with porting my high-speed DDR interface to Altera Cyclone II device. As far as datasheet says, Altera Cyclone II device does not have any dedicated circuitry to support DDR signaling in its Input/Output blocks for DQ pins. The only thing present in hardware is the clock delay circuitry on DQS pins. All other DDR logic is implemented using LUT's and triggers fr...


Does anyone have a NIOS Ethernet Development Kit?

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

My company is attempting to produce a secure switch based on the Altera Stratix II (EP2S60) board. Unfortunatley, Altera no longer sells...

My company is attempting to produce a secure switch based on the Altera Stratix II (EP2S60) board. Unfortunatley, Altera no longer sells the Ethernet Development Kit. We're attempting to build a replica of the daughter card that came with the kit from Altera's designs, but it would be useful to have a working example of the card for comparison purposes. So if anyone has a daughter card bas...


PMC or XMC based on Altera parts (preferably Stratix)

Started by jfh in comp.arch.fpga12 years ago 1 reply

Hi, On a project requiring intensive processing based on VXS boards we are looking at ways of increasing the processing power by using...

Hi, On a project requiring intensive processing based on VXS boards we are looking at ways of increasing the processing power by using a mezzanine board hosting a large FPGA with fast access memory resources. The mezzanine would preferably be an XMC type and PMC as a last resort. We are looking for an Altera based mezzanine as we already have other developments based on Altera FPGAs. Up to...


tri-state in altera

Started by digari in comp.arch.fpga17 years ago 24 replies

hi, i m still in planning phase of my design. i was just looking at xilinx and altera devices. Xilinx provides tri-state buffers as well...

hi, i m still in planning phase of my design. i was just looking at xilinx and altera devices. Xilinx provides tri-state buffers as well as tri-state lines whereas altera doesn't and suggests to use muxs insteed of tri-state buffers. Now assume that i have a bus in my design where lots of drivers are there n driving bus through tri-state buffers. I am just wondering what will happen if i im...


FPGA CAM/TCAM

Started by tony...@gmail.com in comp.arch.fpga16 years ago 1 reply

It looks like Altera's Flex20 is the only FPGA with build in support for instantiate high density CAM/TCAM. The Xilinx approach not as dense...

It looks like Altera's Flex20 is the only FPGA with build in support for instantiate high density CAM/TCAM. The Xilinx approach not as dense as Altera. I am looking for a 70x16K solutions and can't find any good one. FLEX20 is .15 um and 5 years old. But Altera doesn't seem to support CAM in the later Cyclone or Stratix. Does anyone know why? High density CAM seems like a val...