bitstream support for Artix 7 in torc?

Started by Anonymous in comp.arch.fpga3 years ago

Does TORC provide bit stream generation for Artix 7 devices??? Looking at the torc source files, i see classes only for bistrem for Spartan and...

Does TORC provide bit stream generation for Artix 7 devices??? Looking at the torc source files, i see classes only for bistrem for Spartan and Virtex family. Can it be used for Artix device?? If not, will there be support for bitstream generation for any 7 series fpga from Artix and Kintex family???


Xilinx Artix 7 - When?

Started by rickman in comp.arch.fpga7 years ago 12 replies

I am listening to the Xilinx webinar on partial reconfiguration and they say the Artix 7 will be the first "spartan" type device that will be...

I am listening to the Xilinx webinar on partial reconfiguration and they say the Artix 7 will be the first "spartan" type device that will be supported under the ISE software for partial reconfiguration. Anyone heard when the Artix 7 devices are supposed to be in production? Are we talking about a practical time frame such as 6 to 9 months or is it being stated as a year or more? Or have th...


XILINX Artix-7

Started by Bodo in comp.arch.fpga5 years ago 1 reply

Hallo, hat jemand Erfahrungen mit der neuen 7-er Serie von XILINX, speziell mit dem Artix-7? Hat schon jemand Erfahrungen mit dem Demo-Board...

Hallo, hat jemand Erfahrungen mit der neuen 7-er Serie von XILINX, speziell mit dem Artix-7? Hat schon jemand Erfahrungen mit dem Demo-Board des Artix-7? Gr??e Bodo


Artix-7 boards

Started by john in comp.arch.fpga1 month ago 2 replies

Has anyone had any experience of using these...

Has anyone had any experience of using these : http://www.robotshop.com/uk/cmod-a7-35t-breadboardable-artix-7-fpga-module.ht ml?gclid=EAIaIQobChMIkqXI9rje1gIVxZkbCh2l_AkhEAEYASAAEgLo_PD_BwE They aren't in stock yet but maybe some have been shipped. I'm looking for comments on them for use with novice FPGA users. Anything you have to say may be helpful as I'm looking to buy a few of them....


Xilinx Artix-7 availability

Started by Arne Pagel in comp.arch.fpga6 years ago 4 replies

did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I am interested in the XC7A8 or XC7A15 in the...

did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I am interested in the XC7A8 or XC7A15 in the FTG256 Package. regards Arne


how much costs the Artix 7 devices?

Started by Frank Buss in comp.arch.fpga5 years ago 14 replies

Got a newsletter with an advertisment for Xilinx' new Artix 7...

Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm It says "low cost", but how low is low? Is there a distributor who has stocked it or shows at least a lead time? And there is no non-BGA package for it (like TQFP) anymore? -- Frank Buss, http://www.frank-buss.de electronics and more: http://www...


OSERDES as delay regulator e.g. Artix 7

Started by Anonymous in comp.arch.fpga5 years ago

Dear all, as some of you know that the Artix 7 has no ODELAY so I can't handle my delays for the output. But there is a OSERDES as well with MMCM...

Dear all, as some of you know that the Artix 7 has no ODELAY so I can't handle my delays for the output. But there is a OSERDES as well with MMCM or the PLL to manage output pins with different phases e.g. My question is, how can I implement OSERDES fragments so that I can say please create a delay for 3ns before you send the signals.(I know there is a IPcatalog Manager, but I don't know how I...


consulting job / Xilinx Artix MGT POR

Started by Tobias Kahre in comp.arch.fpga5 months ago

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has...

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has to do aurora, the second and third one has to do JESD204b. I am offering a consulting fee for teaching me personally and/or working design of POR up to exchange of comma characters. Cheers, Tobias


Artix-7 tools, ISE vs Vivado

Started by Vladimir Ivanov in comp.arch.fpga3 years ago 4 replies

Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 family? I am interested in the basic...

Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 family? I am interested in the basic synthesis/map/routing/STA steps. Aside from possible speed increase in Vivado, do the synthesis/map/route perform better by generating smaller and/or faster logic? In general, my question is whether it's really worth it learning Vivado in the context of...


XILINX Artix-7 DDR2-RAM-Controller

Started by Bodo in comp.arch.fpga5 years ago 5 replies

Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems" during generation of the simulation...

Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems" during generation of the simulation models from the MIG-tool. Only the top-level of the DDR2-memory-controller is generated in VHDL, the instantiated moduls are generated in Verilog. This is a problem, because I don't have a mixed-language simulator. Are there any experiences using the DDR...


Data transfers between MicroBlaze and VHDL

Started by Robert Higginbotham in comp.arch.fpga5 years ago 11 replies

I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am trying to figure out a way...

I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am trying to figure out a way that I could output the data from the MicroBlaze to a VHDL module and also the reverse transfer. This way I can capture the data, use it in some calculations, and then also pass it back to the MicroBlaze for further use. I am new to Embedded Desi...


Xilinx BULLSHITIX-8, when?

Started by Antti in comp.arch.fpga7 years ago 22 replies

the X-7 roadmap and all device table are no online, and the ARM11 is coming is also all public knowledge, but.. where? in what...

the X-7 roadmap and all device table are no online, and the ARM11 is coming is also all public knowledge, but.. where? in what family? spartan is dead, now is Artix, und Kintex? but where is ARM11? in BULLSHITIX-8 release? I wonder. of course its very interesting to see how much mess Xilinx is able to organize with the 7 series, right now Xilinx online shop list exactly 2 devices of ...


IMX6 Solo - FPGA Module

Started by Mark in comp.arch.fpga2 years ago 1 reply

Hello, I am looking for a module with Freescales iMX6 Solo and an FPGA, maybe an Artix or similar. Anyone know about such module? For now...

Hello, I am looking for a module with Freescales iMX6 Solo and an FPGA, maybe an Artix or similar. Anyone know about such module? For now no other requirements, I will look into details then. Thanks... -- Mark


Migrating Spartan2 design (xnf)

Started by Nico Coesel in comp.arch.fpga6 years ago 4 replies

Because the Xilinx Spartan2 is going to be discontinued in the near future one of my customers asked me to migrate their designs to a newer...

Because the Xilinx Spartan2 is going to be discontinued in the near future one of my customers asked me to migrate their designs to a newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are: - these designs where originally created for the 4000 series using schematic capture (XNF format) then moved to Virtex and finally to Spartan 2. Newer parts where written in VHDL though. - ...


Aligning symbols with IDELAY / ISERDES in Xilinx 7-series devices.

Started by Mike Field in comp.arch.fpga2 years ago 1 reply

Hi, I'm working in Artix-7 and I've got a workable way to adjust the bitslip and IDELAY tap settings to lock onto an incoming TMDS encoded...

Hi, I'm working in Artix-7 and I've got a workable way to adjust the bitslip and IDELAY tap settings to lock onto an incoming TMDS encoded stream, but is there a better way? Currently I count the symbol error rate on the link, and if the rate of bad symbols is greater than 1:2^20 I then move on to a higher delay tap setting. If the delay's tap setting wraps I also assert bi


Low End FPGAs

Started by Rob Gaddi in comp.arch.fpga1 year ago 14 replies

So I'm looking at various platforms for general purpose, fairly low-end FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and...

So I'm looking at various platforms for general purpose, fairly low-end FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera Cyclone V E all have options in the sort of * 170ish IO * Enough logic to do PLDy sort of tasks * $20ish in ~100p quantity. I've used Vivado, and Vivado's got its issues. I've used the latest Quartus Prime, and Quartus Prime's got its issue...