Mark to initialize BRAM

Started by Marco in comp.arch.fpga12 years ago

Hallo, after I have added a software application project into edk, I can choose the option: "mark to initialize bram". If I check it, the...

Hallo, after I have added a software application project into edk, I can choose the option: "mark to initialize bram". If I check it, the software would be located into bram, so after updating bitstream it is loaded as soon as bitstream is downloaded into fpga. But which bram is initialized? the bram connected to ilmb controller? or if I add opb bram controller, the bram connected...


How do I find where P&R has placed my BRAM?

Started by Symon in comp.arch.fpga13 years ago 2 replies

Hi, I use Data2Mem to load a V2Pro BRAM. I'd rather not lock the position of the BRAM just yet, so how do I automate the process of finding...

Hi, I use Data2Mem to load a V2Pro BRAM. I'd rather not lock the position of the BRAM just yet, so how do I automate the process of finding where place and route has put my BRAM? Using FPGA viewer is getting to be a pain. TIA, SYms.


BRAM utilization - how to calculate

Started by Jack in comp.arch.fpga13 years ago 2 replies

dear all I have a question about calculating a BRAM utilzation. I am using XC2VP30 and data sheet says ----------------------------- ...

dear all I have a question about calculating a BRAM utilzation. I am using XC2VP30 and data sheet says ----------------------------- Block SelectRAM+ ----------------------------- 18kb Blocks | Max. BRAM (kb) ----------------------------- 136 | 2448 ----------------------------- and in my MHS file, BRAM is specified as ----------------------------- ... BEGIN lmb_...


Connecting BRAM block to Self designed BRAM controller

Started by Anonymous in comp.arch.fpga10 years ago

Hi all, I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.As a part of assignment, I have to write a verilog/vhdl code for a BRAM...

Hi all, I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.As a part of assignment, I have to write a verilog/vhdl code for a BRAM controller by which we can perform read/write operation on a BRAM block.I have written a desired verilog code for BRAM controller. Also I have added a Bram block to my assembly from pool.But My System assembly does not show any port in my BRAM controller to...


Bram access on FPGA

Started by shamanth in comp.arch.fpga8 years ago

Hi, I am testing a piece of hardware on ML-561(Virtex5). I plan to provide the inputs from a bram pre-loaded with the input cases and the...

Hi, I am testing a piece of hardware on ML-561(Virtex5). I plan to provide the inputs from a bram pre-loaded with the input cases and the outputs will be written to another bram. I want to read the output data stored in that bram to my PC using Xilinx ISE10.1. How can I do that? Please help. Thank you. Shamanth.


Not power of two BRAM size problem

Started by Andrea05 in comp.arch.fpga11 years ago 3 replies

Hi Everybody, I'm using a xc2vp4 FPGA from Xilinx which has 28 blocks of 18Kb (= 504 Kb = 63 KB) of BRAM. The problem is: using EDK is...

Hi Everybody, I'm using a xc2vp4 FPGA from Xilinx which has 28 blocks of 18Kb (= 504 Kb = 63 KB) of BRAM. The problem is: using EDK is only possible to allocate a power of two size (in KB) for the BRAM !!! This means that I can only address 32KB of the 63KB available on FPGA... One possible (bad) solution to use all BRAM can be to create more BRAM controllers each one with a differe...


BRAM initialization / bitstream configuration

Started by Anonymous in comp.arch.fpga9 years ago 2 replies

Hi , The bitstream takes heed of BRAM , so my questions are : * Is it true that all the zeros that we localise in the beginning...

Hi , The bitstream takes heed of BRAM , so my questions are : * Is it true that all the zeros that we localise in the beginning of configurable part ( of bitstream) correspond to BRAM initialization ? * how could i initialize BRAM differently ? Thank you ! M.B


Extracting BRAM data from bitsream

Started by Harish in comp.arch.fpga13 years ago 1 reply

Hello, I am developing a partial reconfigurable system and one of the requirements of my system is that one needs to read and update...

Hello, I am developing a partial reconfigurable system and one of the requirements of my system is that one needs to read and update the contents of the BRAM using the ICAP port. My question is that if I configure Xilinx BRAM for a data width greater than 1, say 8 then will all the 8 bits corresponding to the particular byte be in the same BRAM configuration frame? or will they be distribu...


Adding a bram block to a user defined bram controller

Started by rajiv in comp.arch.fpga10 years ago

Hi all, We have made a bram controller connected to opb bus now we have to connect a bram block to this controller but there is no port...

Hi all, We have made a bram controller connected to opb bus now we have to connect a bram block to this controller but there is no port to do so.Please tell us how can we achieve this?


Extracting BRAM data from configuration Bit stream

Started by Harish in comp.arch.fpga13 years ago

Hello, I am developing a partial reconfigurable system and one of the requirements of my system is that one needs to read and update...

Hello, I am developing a partial reconfigurable system and one of the requirements of my system is that one needs to read and update the contents of the BRAM using the ICAP port. My question is that if I configure Xilinx BRAM for a data width greater than 1, say 8 then will all the 8 bits corresponding to the particular byte be in the same BRAM configuration frame? or will they be distribu...


Accessing BRAM as a SRAM

Started by Marco in comp.arch.fpga12 years ago 7 replies

Hallo, I have a Spartan 3 Starter Board. I should use a BRAM as a SRAM. I have read that BRAM_if_controller should do it. I would know if...

Hallo, I have a Spartan 3 Starter Board. I should use a BRAM as a SRAM. I have read that BRAM_if_controller should do it. I would know if it is possible to connect a dual port ram to the controller. In this way I could access BRAM as 1MB RAM on board though C software and I could also make a sequential reading (hardware, with a counter which generates addresses) on the same BRAM to send...


Writing data to bram with microblaze

Started by mfgunes in comp.arch.fpga10 years ago 1 reply

Hello, I have a microblaze design which includes two bram with microblaze's bram. I want to write the addresses of dip_switches to second...

Hello, I have a microblaze design which includes two bram with microblaze's bram. I want to write the addresses of dip_switches to second bram.How can i write this code in Xilinx Platform Studio SDK? PS:Where can i find detailed documentation about SDK's libraries and their functions? Regards, Fatih Gunes


Xilinx: Initializing BRAM content in the ngc

Started by Sylvain Munaut in comp.arch.fpga11 years ago 1 reply

Hello, I'd like to know if it's possible (and if yes how ?) to initialize BRAM content not directly in the sources, nor in the final .bit...

Hello, I'd like to know if it's possible (and if yes how ?) to initialize BRAM content not directly in the sources, nor in the final .bit file but in the ngc (netlist). The situation is this : I have an IP core that contains several BRAM, some for EDK some for other stuff. Some of them need to be initialized to some values. When I do it "for me", I can do it in the final BRAM file, but...


ppc405 cache using bram

Started by Pit in comp.arch.fpga12 years ago 2 replies

Hi I've got a question concerning the use of BRAM connected to the Dat Cache Unit. Does the processor still use the internal D-Cache Arra when...

Hi I've got a question concerning the use of BRAM connected to the Dat Cache Unit. Does the processor still use the internal D-Cache Arra when BRAM is used? If that were the case, is there any possibility t disable the D-Cache Array, so that the processor is forced to use th connected BRAM Thx in advance Pi


Addressing BRAM in a V2 pro

Started by Mich in comp.arch.fpga12 years ago 6 replies

Hi all, I'm designing a IP core for a Virtex 2 pro board. This IP need to store data in BRAM. I have been searching how I can adress the BRAM...

Hi all, I'm designing a IP core for a Virtex 2 pro board. This IP need to store data in BRAM. I have been searching how I can adress the BRAM with my IP but I haven't found it. Can anyone tell me how you can do this? Thanks Mich


BRAM/XMD strangeness?

Started by Joseph in comp.arch.fpga12 years ago 6 replies

I have a V2P chip and am using both PPCs. Each has its own PLB bus and each PLB bus is connected to a small dual-ported BRAM (amongst...

I have a V2P chip and am using both PPCs. Each has its own PLB bus and each PLB bus is connected to a small dual-ported BRAM (amongst other things). The idea is for them to pass messages to each other through this BRAM, but I was noticing mangled data. The shared BRAM is dedicated to this message-passing (no code or other data lives there). Trying to reduce the problem, I started using XMD...


Q)BRAM VHDL simulation in modelsim

Started by pasacco in comp.arch.fpga12 years ago 2 replies

Hi I have a problem in simulating a memory block (VHDL-written control unit and BlockRAM for Virtex II). BRAM is instantiated as shown...

Hi I have a problem in simulating a memory block (VHDL-written control unit and BlockRAM for Virtex II). BRAM is instantiated as shown below. The problem for me is that the VHDL description of BRAM is not available. The question is that - Can we simulate it in modelsim SE 6.0c? - In case only the BRAM-instantiation is enough to simulate and synthesize, is it meaning that simulator/synth...


PPCs sharing an OCM BRAM

Started by Joseph in comp.arch.fpga12 years ago 3 replies

I have run into a roadblock with my project. Trying to get the PPCs in the V2P to share a BRAM. I have gotten it to work via the PLB bus (both...

I have run into a roadblock with my project. Trying to get the PPCs in the V2P to share a BRAM. I have gotten it to work via the PLB bus (both PPCs with their own bus, each bus connected to the same BRAM), but haven't been able to make it work via the DSOCM. I followed pretty much the same steps to connect both DOCM buses to the same BRAM as I did for the PLB set up, but it seems that writ...


read/write in bram block

Started by Anonymous in comp.arch.fpga10 years ago 2 replies

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component. i have written a verilog...

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component. i have written a verilog code for bram controller (successfully compiled)to interface bram block to opb bus.now i have to write a c code to perform read write operation in bram block.i have written following code #include #include #include


BRAM with output register using ram_style attribute

Started by shantesh in comp.arch.fpga7 years ago 1 reply

Hello, I'm curious to know if there is a way we could tell the synthesizer to use registered mode of BRAM when using ram_style "block"...

Hello, I'm curious to know if there is a way we could tell the synthesizer to use registered mode of BRAM when using ram_style "block" attribute. The registered mode otherwise can be enabled by instantiating a BRAM with DOA_REG, DOB_REG set to 1 and REGCEA, REGCEB set to '1'. For example, the VHDLcode below infers a BRAM. However, it does not enable the registered mode. To g...