min propagation delay in xilinx cpld

Started by guille in comp.arch.fpga17 years ago 12 replies

Hi all, I have a signal that originates at a given device with known timing with respect to the rising edge of a clock: 2 ns min, 8 ns typ,...

Hi all, I have a signal that originates at a given device with known timing with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20 ns max. This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed by the internal CPLD logic. So the timing after going through the CPLD relative to clock (clock does not go through the CPLD) would be like this: tmin = 2 + min(CPLD p...


24 to 32 8-bit PWM outputs

Started by Emtech in comp.arch.fpga15 years ago 9 replies

I have an application where I need to implement 24 or up to 32 PWM outputs (8-bit) and am considering using a small CPLD to handle the PWMs...

I have an application where I need to implement 24 or up to 32 PWM outputs (8-bit) and am considering using a small CPLD to handle the PWMs instead of doing it all in software. This does add a CPLD to the design, but frees the micro do to other things. Any recommendations on the CPLD & CPLD size without completing the VHDL first?


max. sinking current of XC95144xl cpld

Started by nishad in comp.arch.fpga11 years ago 5 replies

My requirement is to replace fifteen 7 segment display drivers using cpld logic. Total I/O connected to display will be 15*8=120. Each pin has...

My requirement is to replace fifteen 7 segment display drivers using cpld logic. Total I/O connected to display will be 15*8=120. Each pin has to sink around 8mA, so Im planning to go for Xilinx XC95288XL CPLD. My doubt is that can the cpld sink 120 lines of 8mA simultaneously?


CPLD mistery. Help.

Started by lc in comp.arch.fpga16 years ago 9 replies

Hello, I implemented in a CPLD a very simple 8bit output port The CPLD connects to the microcontroller bus and this part is simply a latch...

Hello, I implemented in a CPLD a very simple 8bit output port The CPLD connects to the microcontroller bus and this part is simply a latch that is controlled by the address bus and /wr signal. Couldn't be simpler. I had a 'testpoint' out of the CPLD just to check when this latch is gated. All works fine. When I sad to myself that I no longer need the testpoint, and removed the VHD...


Suggestions/Recommendations with CPLD's and Software

Started by Henry in comp.arch.fpga15 years ago 8 replies

I'm looking for some suggestions/recommendations with CPLD's and development software. I'm new to CPLD's and a couple projects of mine...

I'm looking for some suggestions/recommendations with CPLD's and development software. I'm new to CPLD's and a couple projects of mine will involve redesigning existing "though hole" hardware using a CPLD. I've researching some Xilinx products, and believe the 9500 series will do everything I need, as my needs really aren't that great. My only issue with the ISE software is I need...


Analogue like signal interaction within cpld possible ????

Started by Ulrich Bangert in comp.arch.fpga13 years ago 10 replies

Gents, please allow me to confront you with some strange timing behaviour which I have measured with an Xilinx XC95108 cpld. Consider two...

Gents, please allow me to confront you with some strange timing behaviour which I have measured with an Xilinx XC95108 cpld. Consider two well conditioned clock signals of 10 MHz (both having EXACTLY the same frequency) entering the cpld. Inside the cpld each clock signal is divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz signals enter an exclusive-or-gate which del...


Xilinx CPLD XC95144 for Driving Sigma Delta DAC

Started by nba83 in comp.arch.fpga8 years ago 24 replies

hi i would like to drive a Digital to analog converter(AD1933) with a cpld, here is what i'm trying to do: i have a micro controller that...

hi i would like to drive a Digital to analog converter(AD1933) with a cpld, here is what i'm trying to do: i have a micro controller that generate 25Mbps DAC data but is not capable of driving the DAC through high speed SPI(i need over 35MHz spi interface), so i decided to drive the dac with cpld or fpga, since i don't want to increase project cost by using fpga so i prefer to use cpld XC95XX(XC...


Newbie question: fitting in cpld

Started by Stephan Mueller in comp.arch.fpga16 years ago 2 replies

Hi, I have a quit simple question abaut cpld fitting: I'm using a Xilix Coolrunner (XPLA3) CPLD with pin locking and trying to access a...

Hi, I have a quit simple question abaut cpld fitting: I'm using a Xilix Coolrunner (XPLA3) CPLD with pin locking and trying to access a SRAM. If I try to fit my code, the following error message is given by the fitter for some pins: WARNING:Cpld:1081 - Cannot assign signal 'sram_data ' to location '73=FB16_3'. Not enough control terms. Searching the Xilinx answer data base I ca


Best way to write to LUT based CPLD from slow CPU?

Started by Anonymous in comp.arch.fpga12 years ago 3 replies

Hi, I am inexperienced in CPLD design. I am using a slow CPU (PC ISA port) and LUT based CPLD (Altera MAX II) in my design. I...

Hi, I am inexperienced in CPLD design. I am using a slow CPU (PC ISA port) and LUT based CPLD (Altera MAX II) in my design. I implemented many control registers (implemented with D FF) in the CPLD that the CPU will write from time to time. The ISA bus is slow, with a write cycle of several hundred ns. The CPLD is running on 50ns primary clock. I am facing two choices of implementing the...


how to set the ISP mode for programming CPLD?

Started by chi in comp.arch.fpga17 years ago 2 replies

Hello, I need to program CoolRunner CPLD using an embedded controller. How to set the CPLD registers to work in the ISP mode? Please...

Hello, I need to program CoolRunner CPLD using an embedded controller. How to set the CPLD registers to work in the ISP mode? Please explain how to do. Regards, Chi


Essential hazards in CPLD's?

Started by Preben Mikael Bohn in comp.arch.fpga17 years ago 3 replies

Hi NG, are essential hazards avoided in CPLD-designs? If for example I were to design a counter with a subsequent comparator in a CPLD, would...

Hi NG, are essential hazards avoided in CPLD-designs? If for example I were to design a counter with a subsequent comparator in a CPLD, would I be sure that I got no glitches in the output from my comparator? Or would I have to filter the output before I used it in other part of the CPLD? Best regards Preben


FPGA/CPLD group on LinkedIn

Started by Anonymous in comp.arch.fpga13 years ago 8 replies

FPGA/CPLD group on LinkedIn http://www.linkedin.com/e/gis/56713/3CC3BF77FD22 Group for People Involved In the Design and Verification of...

FPGA/CPLD group on LinkedIn http://www.linkedin.com/e/gis/56713/3CC3BF77FD22 Group for People Involved In the Design and Verification of FPGA's and CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD Design/Verification on your Profile to Join. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC)


Radiation + CoolRunner2 CPLD?

Started by Bob in comp.arch.fpga15 years ago 4 replies

Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not designed to be radiation tollerent, but... I would be interested if anyone...

Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not designed to be radiation tollerent, but... I would be interested if anyone reading this has ever radiated a CPLD or know of some CPLD radiation data on the web. I have google searched but found very little. Most ics like 74hc04 parts can take about 10,000 or more rads of total dose (Co60). I hope to do some total dose testi...


CPLD-SPI_flash configuration system problem.

Started by mughat in comp.arch.fpga15 years ago 3 replies

I have a problem width my CPLD-SPI_flash configuration system. I have made a configuration interface for my Spartan 3 FPGA involving a CPLD...

I have a problem width my CPLD-SPI_flash configuration system. I have made a configuration interface for my Spartan 3 FPGA involving a CPLD (CoolRunner 2) and SPI flash (M25P32). My FPGA is set up to serial master configuration mode. The FPGA is generating the clock for the CPLD and the CPLD transfers the data from the SPI flash to the DIN pin on the FPGA. I use the application notes a...


How to extend a pulse width without clock in CPLD!

Started by peterzhu in comp.arch.fpga17 years ago

Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no...

Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no any clock into the CPLD, so the CPLD is pure combination logic. how to extend it in such case? Help me!


FPGA/CPLD Design Group on LinkedIn

Started by cpld-fpga-asic in comp.arch.fpga12 years ago

FPGA/CPLD Design Group on LinkedIn Group for People Involved In the Design and Verification of FPGA's and CPLD's to Exchange Idea's and...

FPGA/CPLD Design Group on LinkedIn Group for People Involved In the Design and Verification of FPGA's and CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD Design/Verification on your Profile to Join. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) 750+ Members http://www.cpldfpga.com (Tip - when first signing up on li...


FPGA/CPLD Design Group on LinkedIn

Started by cpld-fpga-asic in comp.arch.fpga12 years ago 3 replies

FPGA/CPLD Design Group on LinkedIn Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's...

FPGA/CPLD Design Group on LinkedIn Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your Profile. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC and other HDL's as w...


CPLD input

Started by Hans Maier in comp.arch.fpga17 years ago 6 replies

Does a CPLD Input source current ? When I measure the voltage at my CPLD input pin, it is somewhere in the 3V range. When I connect it to...

Does a CPLD Input source current ? When I measure the voltage at my CPLD input pin, it is somewhere in the 3V range. When I connect it to ground, it sources about 50 mA. Is that normal ? I thought an input should not behave like this ..!?


predictable timing for xilinx cpld?

Started by guille in comp.arch.fpga17 years ago 15 replies

Hi all, I'm looking at a design based on a xilinx XCR3256XL cpld. Signals come from different devices (e.g. a CPU), go through the cpld, and...

Hi all, I'm looking at a design based on a xilinx XCR3256XL cpld. Signals come from different devices (e.g. a CPU), go through the cpld, and end on the system's expansion bus. I need to derive the timings for all the signals on this expansion bus, which depend on the timing of the signals at the CPU and on the prop. delays of the cpld. The datasheet says this device has "predictable and ...


Polmaddie Family CPLD and FPGA Teaching Boards

Started by John Adair in comp.arch.fpga11 years ago 5 replies

We finally made an assembly slot and built the 4 remaining Polmaddie CPLD and FPGA boards. These very low cost CPLD and FPGA boards will sell to...

We finally made an assembly slot and built the 4 remaining Polmaddie CPLD and FPGA boards. These very low cost CPLD and FPGA boards will sell to universities and colleges in prices as low as $30-40. One off pricing starts at $60-70. The concept is a bit different to that offered by most development board vendors and we have 5 solutions, from 4 different CPLD/FPGA vendors, allowing you to e...