Rom Implementation in a CPLD

Started by Marco T. in comp.arch.fpga13 years ago 3 replies

Hallo, reading XST user guide it seems that it's not possbile to implement a rom into a cpld, so I have made some experiment with the...

Hallo, reading XST user guide it seems that it's not possbile to implement a rom into a cpld, so I have made some experiment with the following code and ISE has compiled everything without reporting errors. I don't have a real cpld to program, so I would ask if it can function before buying it. type rom_type is array (359 downto 0) of std_logic_vector (15 downto 0); signal ROM : rom_...


CPLD erase??

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Working with a coolrunner2 CPLD. Is there a way to erase whatever has been programmed into the CPLD, without using JTAG?

Working with a coolrunner2 CPLD. Is there a way to erase whatever has been programmed into the CPLD, without using JTAG?


Is a CPLD appropriate for this triple PWM application?

Started by they call me frenchy in comp.arch.fpga15 years ago 24 replies

I am thinking of using a lowcost CPLD as a brain to do various logic functions in addition to driving 3 separate PWM generators. The...

I am thinking of using a lowcost CPLD as a brain to do various logic functions in addition to driving 3 separate PWM generators. The PWM generators will receive their intputs from a state diagram that is cycled through via a pushbutton. Sounds simple. Does anyone object to using a very low cost CPLD for this? Obviously there are many more details involved, like the battery powered, low ...


CPLD development board with 8-bit wide Flash/EEProm

Started by stevem1 in comp.arch.fpga10 years ago 4 replies

I have a custom 8051 RTL core that I want to put into a CPLD on a development board. I also need an external Flash/EEProm memory on the...

I have a custom 8051 RTL core that I want to put into a CPLD on a development board. I also need an external Flash/EEProm memory on the same CPLD development board to run 8051 code from. Are there any CPLD EVM/development boards that come with an 8 bit with Flash/EEProm ? If not I, I will have to attach a socket(for the EEProm), to an existing CPLD board. thanks, -steve


FPGA / CPLD Group on LinkedIn -- Networking Group

Started by cpld-fpga-asic in comp.arch.fpga12 years ago 14 replies

Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You...

Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your Profile. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC and other HDL's as well. Vendors included: Xilinx, Altera,...


FPGA vs CPLD

Started by praveen in comp.arch.fpga16 years ago 14 replies

Hello, What is the differences between FPGA and CPLD? What basis on which i should select. whether to go for cpld or fpga? waiting for ...

Hello, What is the differences between FPGA and CPLD? What basis on which i should select. whether to go for cpld or fpga? waiting for reply with regards praveen


CPLD beginner questions

Started by aleksa in comp.arch.fpga13 years ago 9 replies

I'm currently using GALs (16V8-18V8-22V10), but my current board requires 4 GALs and I would like to replace them with one CPLD which would...

I'm currently using GALs (16V8-18V8-22V10), but my current board requires 4 GALs and I would like to replace them with one CPLD which would also replace 4 other general ICs. I've never had the guts to try CPLD because I thought they were complicated to learn, hard to solder and most of all, impossible to programm without some $$$. Now I think different, but am unsure... I've choosen ...


NVRAM design in CPLD

Started by jay in comp.arch.fpga13 years ago 3 replies

Hi all, For the ram implied in a CPLD design, will the data written in it remain after power off? I have a small rom in my curent CPLD...

Hi all, For the ram implied in a CPLD design, will the data written in it remain after power off? I have a small rom in my curent CPLD design, occasionally I need change the content inside, instead of reprogramming it, I want something like a nvram that I can update through the uP dynamicallly. Thanks, Jay


cpld 9572 xilinx

Started by melvin in comp.arch.fpga12 years ago 2 replies

Currently i am doing my final year project on xilinx cpld 9572 How do we can access registers in this cpld using...

Currently i am doing my final year project on xilinx cpld 9572 How do we can access registers in this cpld using vhdl .......


PROBLEMS WITH COOLRUNNER XPLA3

Started by Anonymous in comp.arch.fpga15 years ago 5 replies

hi im using digilab XCR development board which has Xilinx XCR3064 CPLD. I/O pins in this CPLD are said to be tristate. but when im trying to...

hi im using digilab XCR development board which has Xilinx XCR3064 CPLD. I/O pins in this CPLD are said to be tristate. but when im trying to use them as tristate its not working as one? i mean i want one of the I/O pin to go high impedance but its not? can any one tell me how can i make I/O pin in CPLD high impedance?


delay using integrator

Started by Sonali in comp.arch.fpga15 years ago 1 reply

I want to use the output of a R-C integrator as a delayed input to CPLD (inside there is a XOR gate and counter logic). It worked OK when I...

I want to use the output of a R-C integrator as a delayed input to CPLD (inside there is a XOR gate and counter logic). It worked OK when I use discrete XOR IC 4070. But for same R-C values it doesn't works with CPLD. Is is due to the fact that analog input (sawtooth from integrator) has given to CPLD? Is comparator after integrator is one of the solution? Suggest other methods for creating...


could I drive Altera MAX II CPLD with LSTTL outputs?

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

The MAX II can tolerate 3.3V input, I believe. I read some TTL data sheets but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V)...

The MAX II can tolerate 3.3V input, I believe. I read some TTL data sheets but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V) only. The max VOH is usually not provided. Could I drive the CPLD i/o pins directly, with the LSTTL outputs? I will try to use some LVTTL to interface the CPLD, if LSTTL are not qualified. Thank you. vax, 9000


MAX7000S CPLD tri-state OE delay

Started by Andrew Holme in comp.arch.fpga16 years ago

I'm interfacing a 2kx8 15ns CMOS SRAM (IDT6116SA15TP) to an Altera EPM7128SLC84-15 CPLD to implement a very simple CPU. Data and program...

I'm interfacing a 2kx8 15ns CMOS SRAM (IDT6116SA15TP) to an Altera EPM7128SLC84-15 CPLD to implement a very simple CPU. Data and program will be stored in the SRAM which is pre-loaded via JTAG using JAM STAPL. My problem is the CPLD output buffer enable / disable delays (tZX / tXZ) which - being of the order of 7ns - are going to cause data bus contention. I'm driving the lpm_bustri OE sig...


frequency multiplication

Started by Jim in comp.arch.fpga17 years ago 4 replies

Hi, for a re-desing i'd like to omit a 'standard' pll with counters etc. used for frequency multiplication, by a cpld. Among other things, the...

Hi, for a re-desing i'd like to omit a 'standard' pll with counters etc. used for frequency multiplication, by a cpld. Among other things, the cpld has to perform a 128x frequency multipliction 48KHz to 6144Khz). Some (many) cpld's have on-board pll's but these are not usefull because they are inteded for clock distribution and the lowest operating frequency is much lower than 48KHz. T...


ML403 FPGA and CPLD

Started by Marco T. in comp.arch.fpga14 years ago

Hallo, I would connect virtex-4fx and cpld to test an i2c slave peripheral. Into virtex-4 I have programmed a small system with microblaze,...

Hallo, I would connect virtex-4fx and cpld to test an i2c slave peripheral. Into virtex-4 I have programmed a small system with microblaze, opb_i2c, and some other peripherals. Into cpld I would program a small i2c custom slave peripheral. Is it possible to realize, otherwise I have troubles due to bus sharing with flash and ram? Many thanks in advance Marco


how interfacing of cpld and cpu done?

Started by Anonymous in comp.arch.fpga13 years ago 1 reply

please give me information about inerfacing of cpld xc9572 & cpu

please give me information about inerfacing of cpld xc9572 & cpu


Adding a Delay2

Started by Paul Gray in comp.arch.fpga16 years ago 3 replies

I need to delay one of the output signals from my cpld by 80nS. The clock frequency of our board is 48MHz. Im using the altera quartus...

I need to delay one of the output signals from my cpld by 80nS. The clock frequency of our board is 48MHz. Im using the altera quartus software. We have data and address lines and a chip select going into the cpld. The outputs are open drain. When the data and address lines are changed from a Low to a High state they take about 60ns to rise up on the ouputs of the CPLD. The problem is...


cpld version?

Started by Anonymous in comp.arch.fpga14 years ago 16 replies

I want to order a xilinx xc9536 cpld. In one catalog I found the following 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 15ns,...

I want to order a xilinx xc9536 cpld. In one catalog I found the following 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 15ns, 100MHz XC9536-15PC44C. 384-8980 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 10ns, 100MHz, 3.3V (IND TEMP) XC9536XL-10PC44C 384-9016 What are the 15ns and 10ns respectively refer to ?


PLL in CPLD

Started by Kriki in comp.arch.fpga16 years ago 1 reply

I need to program a digital PLL in a CPLD. I tryed to use an external Clock Generator @ 24.576 MHZ, but the data signal is not exactly that...

I need to program a digital PLL in a CPLD. I tryed to use an external Clock Generator @ 24.576 MHZ, but the data signal is not exactly that frequency. So can anyone help me with that problem ???


ANN CPLD add-on module for Nintendo DS game console

Started by Antti in comp.arch.fpga13 years ago 2 replies

Hi I have a few (5 at the moment) of NDS CPLD boards manufactured, the preliminary user manual is...

Hi I have a few (5 at the moment) of NDS CPLD boards manufactured, the preliminary user manual is here http://code.google.com/p/nds-homebrew/downloads/list from that public google project are also available VHDL examples and C code for this CPLD board the C code example includes Xilinx XSVF player adapter to NDS ARM9 It fits the NDS slot-2 and can be reprogrammed in system, there ar...