DPLL in CPLD

Started by Jim in comp.arch.fpga17 years ago 5 replies

Hi all, i need to implement a (D) PLL in a CPLD. Purpose is to multiply a frequency of 32KHz to 4,096KHz. On board PLL's don't work since...

Hi all, i need to implement a (D) PLL in a CPLD. Purpose is to multiply a frequency of 32KHz to 4,096KHz. On board PLL's don't work since the freq. is very low How do i start? Jim


CPLD program editing

Started by abhi in comp.arch.fpga15 years ago 2 replies

Hi Group, I need to edit a program loaded in a CPLD.I can read a JDEC file from the CPLD.How can I convert that file into a readable program...

Hi Group, I need to edit a program loaded in a CPLD.I can read a JDEC file from the CPLD.How can I convert that file into a readable program which I can edit? Thanks


CPLD/FPGA with Linux

Started by Scorpiion in comp.arch.fpga11 years ago 11 replies

Hi, I have just started out with some VHDL in school and would like to have something at home to play with. I'm not sure of CPLD vs FPGA for my...

Hi, I have just started out with some VHDL in school and would like to have something at home to play with. I'm not sure of CPLD vs FPGA for my use, but CPLD feel more suited for smaller projects I guess. My question is how Linux is supported as developmentplatform? (I have linux on my computers at home and want to be able to us them as hostsystem, at school we use some older version of a program ...


100 Mbit manchester coded signal in FPGA

Started by Michael Dreschmann in comp.arch.fpga14 years ago 37 replies

Hi all, we are trying to implement a 100 MBit communication link witch uses manchester coding. The signal is generated by a CPLD (xc2c64a) and...

Hi all, we are trying to implement a 100 MBit communication link witch uses manchester coding. The signal is generated by a CPLD (xc2c64a) and we hope we can receive it with an FPGA (Virtex4 for example). Because the CPLD design will work at 2.5V and should use minimal power (sensor node) my question is if it is possible to use a crystal with a NOT-gate in the CPLD for generating the oszil...


How to extend a pulse width without clock!

Started by peterzhu in comp.arch.fpga17 years ago 6 replies

Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no...

Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no any clock into the CPLD, so the CPLD is pure combination logic. how to extend it in such case? Help me!


Getting started with Xilinx CPLD

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

Hello, I have a need for something faster than a microcontroller and decided on using logic IC's to do it. Well I don't need to say why I...

Hello, I have a need for something faster than a microcontroller and decided on using logic IC's to do it. Well I don't need to say why I next decided to use programable logic instead. I've have never used a PLD before. After visting Xilinx web site I ordered the CPLD Design Kit to get started. Lets see know, all I have to do is program my logic schematic into one of these CPLD devices!...


Programming flash connected to CPLD via JTAG

Started by woko in comp.arch.fpga16 years ago 6 replies

Hello! I want to revitalise a question at was asked in 2001, because I hope something changed during the time. How can a AT49LV001 flash by...

Hello! I want to revitalise a question at was asked in 2001, because I hope something changed during the time. How can a AT49LV001 flash by programmed through a XC9536XL CPLD and its JTAG-connector with really low cost? All address, data and control pins are connected to the CPLD, so ISP via JTAG should be possible.I'm sure there are lots of tools available at this time for programmin...


MAX II CPLD and I2S Clock divider jitter

Started by Mark in comp.arch.fpga10 years ago 4 replies

I have MAX II CPLD with clock of 24.576 MHz as input coming from the external crystal oscillator. This clock is used inside the CPLD to generate...

I have MAX II CPLD with clock of 24.576 MHz as input coming from the external crystal oscillator. This clock is used inside the CPLD to generate sub clocks, thats no problem. Also, my design needs to output the incoming 24.576 MHz clock as it is to the external Audio DAC through one of the I/O pins. So I have three options. Which one is the best option for lowest possible jitter? 1) Output...


How to deal with unavoidable setup time violation in CoolRunner II cpld?

Started by Anonymous in comp.arch.fpga14 years ago 7 replies

Hi, I apologize if this question is too stupid... basically I want to build a protocol analyzer with a CoolRunner II cpld. the CPLD will watch...

Hi, I apologize if this question is too stupid... basically I want to build a protocol analyzer with a CoolRunner II cpld. the CPLD will watch the bus line and extract data. I have passed behaviorial simulation and fitted the device. but post-fit timing simulation gives me some setup time violations and the output goes to X afterwards. I read document that says ASYNC_REG can be used but it i...


Clock loading in XC9572 CPLD

Started by Naimesh in comp.arch.fpga16 years ago 3 replies

Hello, I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i. I am observing a illogical problem. All my flip flops are...

Hello, I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i. I am observing a illogical problem. All my flip flops are negative edge triggered but some how even if the edge on the clock comes cpld doesnt recognize it. So I made a simple flip flop where at Power On Reset I am clearing it and at the edge of the clock I am setting it to 1. Even then I was not able to see t...


EMC and Shared SRAM/FLASH Bus

Started by Matt in comp.arch.fpga16 years ago 3 replies

Hi, I'm a student new to fpga design and am trying to design a board with a spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II...

Hi, I'm a student new to fpga design and am trying to design a board with a spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II cpld; all sharing a common address/data bus. I'm interested in accomplishing the following: 1. The ability to configure the spartan-3 from FLASH using the CPLD. 2. Access to SRAM, FLASH, and a few memory mapped cpld registers using the Xilinx ED...


Error while downloading prodram on CPLD

Started by sanika in comp.arch.fpga12 years ago 3 replies

Hello, I am using XC9572XL High Performance CPLD. Just for a try i wrote simple program just to equate input to output. The code is synthesized...

Hello, I am using XC9572XL High Performance CPLD. Just for a try i wrote simple program just to equate input to output. The code is synthesized but when I try to download code on CPLD through iMPACT it fails. Then I checked with all other options. Device is detected and erased properly but 1. Checksome fails 2. functional test fails. Error -- ERROR:iMPACT:431 - '1':No vectors present. ...


Replacing Logic with an FPGA/CPLD in a 510K device.

Started by hamilton in comp.arch.fpga8 years ago 2 replies

Does anyone have some good links on FDA requirements for replacing TTL logic with an FPGA/CPLD ? This is for a Class 3 device. Does the...

Does anyone have some good links on FDA requirements for replacing TTL logic with an FPGA/CPLD ? This is for a Class 3 device. Does the FPGA/CPLD design files constitute "firmware" and needs to be tested the same way as firmware ? Thank you hamilton


CPLD programming sequence XC9500

Started by gopal_amlekar in comp.arch.fpga11 years ago 2 replies

Hello, I want to understand a few things about CPLD programming. There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table 7...

Hello, I want to understand a few things about CPLD programming. There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table 7 on page 11 shows the device configuration sequence to transfer a bit stream. Similarly, is there any sequence for CPLD XC9500? What I understood is that the .jed file is transferred instead of .bit file in the SHIFT-DR state. Is this correct? Aft...


ISE 8.2 & XC9500XL family

Started by Jozsef in comp.arch.fpga14 years ago 3 replies

Hello, as many people over this world, I have a problem. The problem is the connection beetween a CPLD and the WEBPACK ISE 8.2.03...

Hello, as many people over this world, I have a problem. The problem is the connection beetween a CPLD and the WEBPACK ISE 8.2.03 software. Simptoms like very static: I have an Parallel Cable III, the ISE software, and a XC9500XL family CPLD. The Impact cannot recognise the CPLD, for example a simple XC95144XL showed five unknown device in the JTAG chain on automatic JTAG chain initialize...


which Altera CPLD?

Started by Manfred Balik in comp.arch.fpga15 years ago 1 reply

I want to use an Altera CPLD to do the interface between an ISA-Bus and a Cyclone II-FPGA. The CPLD should satisfy the criteria of the ISA-Bus...

I want to use an Altera CPLD to do the interface between an ISA-Bus and a Cyclone II-FPGA. The CPLD should satisfy the criteria of the ISA-Bus timing to enable/disable the FPGA and do the level-conversion between the 5V ISA-Bus-levels and the logic levels of the FPGA (3,3V or 2,5V or 1,8V). I found this Altera CPLDs: MAX II doesn't support 5V I/Os MAX 3000A MAX 7000B doesn't support 5...


EPLD Lattice Prog Problem

Started by max_mont in comp.arch.fpga15 years ago

Hi all, I'm developping an application on PowerPC to programm a Lattice EPLD. For that, I'm using ispVM Lattice player. When I programm the...

Hi all, I'm developping an application on PowerPC to programm a Lattice EPLD. For that, I'm using ispVM Lattice player. When I programm the CPLD which is already programmed by JTAG connector, all is running. But when I programm a new CPLD which has never been programmed, the programmation failed and I have message from VME player to tell that TDO signal is wrong. The CPLD is in a J...


very slow pull-up with CPLD design

Started by Anonymous in comp.arch.fpga15 years ago 2 replies

We are using a Lattice LC4256V CPLD for a new design and we're having some problems with open drain outputs + 5V pullups. We've debuged...

We are using a Lattice LC4256V CPLD for a new design and we're having some problems with open drain outputs + 5V pullups. We've debuged and removed items from the system to the point where we have the single CPLD (pins configured 3.3v CMOS open drain) connected to a 4.7K resistor to +5V. We configured the pins to output a 4MHz square wave for testing. When we hook a scope up to the pins, w...


Atmel CPLD development tools for verilog

Started by sri in comp.arch.fpga16 years ago

Hi, Currently I have verilog design files ready for a CPLD implementation and am planning to use a Atmel AT15xx series CPLD. But I am...

Hi, Currently I have verilog design files ready for a CPLD implementation and am planning to use a Atmel AT15xx series CPLD. But I am having difficulty in finding the right Atmel development software. As per the Atmel website, Prochip supports Verilog, but when installed I am not able to compile the Verilog design. Is there any other tool I can use to get the edif file from my Verilog...


programming a LC5512MB using the IEEE1532 extension

Started by Burkhard Schermer in comp.arch.fpga16 years ago 1 reply

Hi all, I tried to program a Lattice CPLD LC5512MB via the Xilinx parallel cable by using Xilinx iMPACT in batch mode with an ISC-file. The...

Hi all, I tried to program a Lattice CPLD LC5512MB via the Xilinx parallel cable by using Xilinx iMPACT in batch mode with an ISC-file. The programming perfectly worked with an empty CPLD but if the CPLD already was programmed , strange things was happened - all Bits was programmed with zeros. It looks like as the ERASE OpCode in the LATTICE 1532-BSDL-file would not work. Does somebody k...