ISP for XCR3256XL

Started by chi in comp.arch.fpga17 years ago

hai, I am new to the CPLD programming. I have to upgrade the CPLD(XCR3256XL) program using embedded controller. How commands like ISPEN,...

hai, I am new to the CPLD programming. I have to upgrade the CPLD(XCR3256XL) program using embedded controller. How commands like ISPEN, FERASE etc., will be called? Can anyone explain? Thanks in advance, Chi


Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell

Started by Eric in comp.arch.fpga12 years ago 4 replies

Hello all, knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can I convert this into a Xilinx CPLD Macrocell? Example:...

Hello all, knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can I convert this into a Xilinx CPLD Macrocell? Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD Device (number of Macrocells) would be sufficient? Haven't found any reference at xilinx or google. Thanks for any feedback, Richard


FPGA/CPLD Basics

Started by Jack// ani in comp.arch.fpga16 years ago 5 replies

Hi all, Is there any tutorial on web, where I can learn about working and architecture of FPGA and CPLD? Google turned out to be useless....

Hi all, Is there any tutorial on web, where I can learn about working and architecture of FPGA and CPLD? Google turned out to be useless. Someone out there maybe is having some helpful pointer. Any suggestion regarding reference/text books is also appreciated. TIA


can JTAG port of CPLD gets damaged?

Started by mohan in comp.arch.fpga14 years ago 2 replies

i am using altera cpld.using quartus 2 tool to programme it through byte blaster cable. I have installed drivers for the cable.made connections...

i am using altera cpld.using quartus 2 tool to programme it through byte blaster cable. I have installed drivers for the cable.made connections intact. i am getting error as "Unable to scan device." My assusmption was may be because of loose contacts this error was coming.but connections are intact.supply are proper,still i cann't programme cpld. is there any possibility of jtag port of cpl...


why use an FPGA when a CPLD will do ??

Started by Matt Clement in comp.arch.fpga15 years ago 16 replies

Hey guys/gals What are the advantages and disadvantages of using a CPLD instead of using an FPGA for a design? Thanks

Hey guys/gals What are the advantages and disadvantages of using a CPLD instead of using an FPGA for a design? Thanks


good starter kit

Started by cpex in comp.arch.fpga17 years ago 5 replies

Hello, I am a computer engineering student and I am looking to do a project which will require a FPGA or CPLD. I will need something with > ...

Hello, I am a computer engineering student and I am looking to do a project which will require a FPGA or CPLD. I will need something with > 70 general IO pins. I am looking for a development board that will give me an expansion port to plug it into my project. I want something less than $100 perferably less than $50. I am currently considering the CPLD design kit from XILINX which has XC2


GAL,PAL,PLD, CPLD,FPGA

Started by Anonymous in comp.arch.fpga16 years ago 7 replies

GAL,PAL,PLD, CPLD,FPGA, (what else...?) GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD :...

GAL,PAL,PLD, CPLD,FPGA, (what else...?) GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD : Complex Programmable Logic Device FPGA : Field Programmable Gate Array Can someone explain with comparison what is the difference between all these GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? Can all these units can be programmable with VH...


CPLD + =?UTF-8?B?wrVDIHdpdGggcmVhc29uYWJseS1wcmljZWQgdG9vbHM/?=

Started by H. Peter Anvin in comp.arch.fpga14 years ago 12 replies

Hi all, I have a potential (hobby) project, where I'm looking at needing, in effect, a CPLD and a µC that can share memory. +5 V I/O...

Hi all, I have a potential (hobby) project, where I'm looking at needing, in effect, a CPLD and a µC that can share memory. +5 V I/O tolerance is necessary (for about 52 signals coming into the board), and I would like to keep the power supply complexity to a minimum since I'm really a software guy and don't particularly trust my board layout skills. Anyway, I was looking at using ...


[CPLD] Novice

Started by novato in comp.arch.fpga16 years ago 3 replies

Hello: Sorry by my badly english, I have it very oxidized. I?m Spanish. My question is the following one, is become fond of to the...

Hello: Sorry by my badly english, I have it very oxidized. I?m Spanish. My question is the following one, is become fond of to the electronic and is beginning with the CPLD subject (I want to have level to begin with FPGA, but I have left myself very great); I?m beginning to program them with VHDL and to understand its operation, I have several files *.jed of different devices. There...


Hve to know the pin connection between cpld and fpga in my design

Started by senthil in comp.arch.fpga16 years ago

Hi Friends, In my board i have SRAM, Spartan-3 FPGA ,CPLD Xc95144xl and PC104 Connector (ISA bus header). I want to pass the data stored in...

Hi Friends, In my board i have SRAM, Spartan-3 FPGA ,CPLD Xc95144xl and PC104 Connector (ISA bus header). I want to pass the data stored in SRAM to PC104 . in between that with the help of spartan-3 only data stored in SRAM. ____ ______ ______ _______ |pc | | | | | | | |104 | | CPLD | |SP-3 | | SRAM |


I do not know this !

Started by Ali in comp.arch.fpga14 years ago 3 replies

I like to start FPGA but I have access to a CPLD traning kit . I would like to know : 1-If I start with CPLD (XC9572 the training kit has...

I like to start FPGA but I have access to a CPLD traning kit . I would like to know : 1-If I start with CPLD (XC9572 the training kit has it ) can I later work with FPGA (Spartan 2,3) ? 2-Does these two have much defferent Hardware design ? 3-Are ISE & VHDL have much defference ?


CPLD CoolRunner-II - IO current limited to 8mA?

Started by Anonymous in comp.arch.fpga15 years ago 4 replies

Hello, I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). But from the datasheet I get that the current is limited to I_OH...

Hello, I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). But from the datasheet I get that the current is limited to I_OH and I_OL = 8mA. Is this right? Means this that I couldn't use this LED with 1.8V? Have I to operate the LED with 8mA and the corresponding voltage (using a resistor in series)? Regards Deniz


detailed description on the archetecture of FPGA's/CPLD's

Started by Guru Prasad in comp.arch.fpga15 years ago 3 replies

Hello, I am verry new to this Field and i would be verry happy if anybody would sujjest me a link or any document which gives me an idea on...

Hello, I am verry new to this Field and i would be verry happy if anybody would sujjest me a link or any document which gives me an idea on what an FPGA/CPLD is and its arcitecture,how a vhdl code is actually implmented in these... Regards, Guru Prasad


How to add clock delay in CPLD?

Started by rat in comp.arch.fpga17 years ago 8 replies

Hi,friends, To meet the Tsu requirement in my design, I think I should try to add some clock delay to the input register, how can I do that in...

Hi,friends, To meet the Tsu requirement in my design, I think I should try to add some clock delay to the input register, how can I do that in CPLD? (not FPGA, without PLL,DLL) Thanks!


Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT

Started by nshrestha in comp.arch.fpga15 years ago 2 replies

I was trying to program xc2c256_tq144 (CoolRunner II) CPLD using ISE Project Navigator SW version 7.1.04i. I used parallel III cable provided by...

I was trying to program xc2c256_tq144 (CoolRunner II) CPLD using ISE Project Navigator SW version 7.1.04i. I used parallel III cable provided by Digilent to program the CPLD. But I am getting error "iMPACT 583 - '1': The idcode read from the device does not match the idcode in the BSDL file". I tried to view BSDL file but I don't have a clue as to how to modify device IDCODE so device id and...


Soft failures (?) 9536XL

Started by Josep Duran in comp.arch.fpga17 years ago 9 replies

I have a small circuit using the 9536XL CPLD. The complete machine uses 64 of such circuits. I have tested it on the lab and everything works...

I have a small circuit using the 9536XL CPLD. The complete machine uses 64 of such circuits. I have tested it on the lab and everything works just fine. The problem is the other day, while at the client premises, I saw something wrong with one of the boards. The CPLD stopped responding to the commands sent by the computer. As I had no test equipment available, I just tried to send some re...


74 logic to CPLD. how easy for a Newbie?

Started by Carl in comp.arch.fpga17 years ago 14 replies

Hi, My apologies if this is not the most appropriate group for this query. I am starting to have great difficulty sourcing some 74 logic...

Hi, My apologies if this is not the most appropriate group for this query. I am starting to have great difficulty sourcing some 74 logic parts from my design in SMD (at least in small volumes). As I now have the chance to make a new PCB revision I am wondeing if I couldn't do away with the logic all together and use a PLD (CPLD). So for those who know the learning curve well, I ha...


clock division / multiplication in xilinx cpld

Started by Anonymous in comp.arch.fpga16 years ago 4 replies

I have a design using a xilinx xc9500xl cpld. This project is a patch to an existing project and so not all the signals I need are...

I have a design using a xilinx xc9500xl cpld. This project is a patch to an existing project and so not all the signals I need are readily available. I have clk/2 and clk*2, but I need clk. The desired waveforms are: clk*2: -.-.-.-.-.-.-.-. clk: --..--..--..--.. clk/2: ----....----.... My original, not-well-thought-out plan was to simply take clk*2 and divide the frequency down si...


Where can I buy Cheap MAX II CPLD?

Started by Zimmer in comp.arch.fpga16 years ago

Hi Everyone, Can anybody let me know where to buy the EPM1270 TQFP CPLD in cheap price? I've checked altera.com, the online wholesale price is...

Hi Everyone, Can anybody let me know where to buy the EPM1270 TQFP CPLD in cheap price? I've checked altera.com, the online wholesale price is $4.25/pc for 500K units. But the distributer would charge me over $24 for 10 pc. (ebay.com is not a good site for the stable supply) Any advice appreciated! -Zimmer


CPLD + CAN bus

Started by Falk Salewski in comp.arch.fpga16 years ago 16 replies

Hello everybody, I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To make it easy I would like to use a ready to use CAN-bus...

Hello everybody, I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To make it easy I would like to use a ready to use CAN-bus driver chip (as much of the protocol implemented as possible). Any suggestions? How many of the CPLD resources does it take to initialize/communicate with the CAN-bus driver chip? Thanks for your help! Falk Salewski Embedded Software Labora...