Small FPGA

Started by Sylvain Munaut in comp.arch.fpga16 years ago 13 replies

Hello, I'd like to find a really small FPGA that I could solder by hand, like in a VQ44 or VQ64 package. Ideally, it should only require...

Hello, I'd like to find a really small FPGA that I could solder by hand, like in a VQ44 or VQ64 package. Ideally, it should only require a single 3.3v supply, but a dual supply core/io would be OK too if really necessary. I really don't need many logic probably as few as 500 LE. I tried the XC9500 CPLD line from xilinx but it seems my application doesn't fit CPLD well, I basically nee...


CPLD speed/temperature equivalent

Started by Manfred Balik in comp.arch.fpga14 years ago 1 reply

I have a ALTERA MAX3000A CPLD with two inscriptions: EPM3256AFC256-7 --> commercial temp, speed grade 7 and EPM3256AFI256-10 --> industrial...

I have a ALTERA MAX3000A CPLD with two inscriptions: EPM3256AFC256-7 --> commercial temp, speed grade 7 and EPM3256AFI256-10 --> industrial temp, speed grade 10 I bought the industrial one. Are this two CPLDs equivalent??? If yes -> if I buy the commercial, speed grade 7 - is this CPLD equivalent to the industrial temp, speed grade 10??? Thanks for your answers in advance, Manfred


Re: Newbie question: fitting in cpld

Started by Stephan Mueller in comp.arch.fpga16 years ago

Hi Marc, many thanks for your suggestions! It worked, but afterwards I got some problems with product terms. That's why I switched to buffers...

Hi Marc, many thanks for your suggestions! It worked, but afterwards I got some problems with product terms. That's why I switched to buffers now. They can be located anywhere in the CPLD, so that I am not that restricted anymore.. Greetings, Stephan "Marc Randolph" schrieb im Newsbeitrag news:1103027985.683504.75530@f14g2000cwb.googlegroups.com... > Stephan


FPGA programming via Slave-Serial-Mode

Started by C.Jesko in comp.arch.fpga16 years ago 4 replies

We are programming an FPGA (Spartan2E) via a CPLD in Slave-Serial-Mode. The CPLD loads the bitfile from FLASH and writes it to the FPGA. When...

We are programming an FPGA (Spartan2E) via a CPLD in Slave-Serial-Mode. The CPLD loads the bitfile from FLASH and writes it to the FPGA. When we are programming a bitfile into an FPGA without "MicroBlaze" via CPLD, the programming is always successful, after programming the DONE-Pin goes high and the application is running. Now our problem: when programming a bitfile including "MicroBlaze" v...


XC9572 Readback

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

Hi! I am facing a problem regarding Xilinx CPLD Readback. One of our engineers left the country who designed the system back in 2000 and...

Hi! I am facing a problem regarding Xilinx CPLD Readback. One of our engineers left the country who designed the system back in 2000 and is out of touch now. I have no idea where are the original design files and the JEDEC files. However I do have two or 3 boards which have the working CPLD with the code I need. I have no experience with a readback feature. Can anyone help in this rega...


Interesting question on CPLD

Started by himassk in comp.arch.fpga16 years ago 4 replies

Hi, can we disconnect the power suppy to some Macrocells which are not using in the design or functionality for a perticular...

Hi, can we disconnect the power suppy to some Macrocells which are not using in the design or functionality for a perticular time or all the time, So that I can save the overall power consumption Is there any arrangement is available in the CPLD to cut off the power supply for unused Macrocells by using clock gating. Please Answer this. Regards, ...


What About CPLD Standardization ?

Started by Chris_S in comp.arch.fpga18 years ago

In a previous post I got into the subject of CPLDs going obsolete. Hey folks, what ever happened to standardization with logic anyway? ...

In a previous post I got into the subject of CPLDs going obsolete. Hey folks, what ever happened to standardization with logic anyway? Remember 7400 series, 16V8's, and 22V10's ? Those were logic standards with multi-source vendors and common pinouts. Why is it still necessary for every CPLD vendor on the planet to put out all proprietary families? Why does standardization not apply to C...


Motion controller design with CPLD

Started by Leeinhyuk in comp.arch.fpga16 years ago 1 reply

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or...

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or application note. Best regards IH Lee leeih@chollian.net


Motion controller design with CPLD

Started by Leeinhyuk in comp.arch.fpga16 years ago 1 reply

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or...

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or application note. Best regards IH Lee leeih@chollian.net


Motion controller design with CPLD

Started by Leeinhyuk in comp.arch.fpga16 years ago

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or...

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or application note. Best regards IH Lee leeih@chollian.net


Motion controller design with CPLD

Started by Leeinhyuk in comp.arch.fpga16 years ago

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or...

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have design examples or application note. Best regards IH Lee leeih@chollian.net


isplever and GAL

Started by Strelnikov in comp.arch.fpga15 years ago 4 replies

Hi everybody, I bought the isplever 5.0 to develope a project with a lattice cpld, serie ispmach. I used the schematic approach, and after...

Hi everybody, I bought the isplever 5.0 to develope a project with a lattice cpld, serie ispmach. I used the schematic approach, and after some attempts, everything went well, and I got my cpld programmed and working. Now I need to put down a simple logic with a GAL16V8, using the schematic, but despite everybody says the ISPlever environment is simple and user-friendly, with some shame...


CPLD Pad File

Started by akshat in comp.arch.fpga13 years ago 2 replies

I am trying to generate a CPLD pad file using a dummy module and ucf. Translate process gives the following error: ERROR:NgdBuild:605 -...

I am trying to generate a CPLD pad file using a dummy module and ucf. Translate process gives the following error: ERROR:NgdBuild:605 - logical root block 'test' with type 'test' is unexpanded. Symbol 'test' is not supported in target 'xbr'. Any idea what might be wrong??


Xilinx CPLD configuration under Linux ?

Started by Brian Dam Pedersen in comp.arch.fpga16 years ago 6 replies

Hi All Sorry for this being slightly off-topic, but this was the closest group I could find. I need to configure a xilinx XC9536XL under...

Hi All Sorry for this being slightly off-topic, but this was the closest group I could find. I need to configure a xilinx XC9536XL under linux. I've tried using naxjp, which can identify the CPLD correctly (sort of - it identifies it as being a cs48 when it actually is a pc44 ..), but when I try to program it I get $ ./naxjp -auto xc9536xv_pc44:/home/brian/projects/extensionboar...


System ACE equivalent for CPLDs

Started by Benjamin Todd in comp.arch.fpga15 years ago 13 replies

I know this isn't exactly comp.arch.cpld... does anyone know of a COTS solution for programming a (Xilinx) CPLD without using PC + Windows +...

I know this isn't exactly comp.arch.cpld... does anyone know of a COTS solution for programming a (Xilinx) CPLD without using PC + Windows + Impact etc etc. (a stand alone chunk of hardware with a way for me to give it a set of bit files and a Program button would be nice) I want to load one bit-file into a device to run a test, then once the test is finished load a second bit-file - b...


bidirectional bus

Started by nobody in comp.arch.fpga11 years ago

An eight bit bus on the PCB is used for both programming an FPGA, XC3S250EVQ100, as a slave parallel configuration from a CPLD, XC2C64AVQ100,...

An eight bit bus on the PCB is used for both programming an FPGA, XC3S250EVQ100, as a slave parallel configuration from a CPLD, XC2C64AVQ100, and secondarily carry information back to the CPLD after programming. This programming configuration releases the done pin, however unable to drive an external set of LEDs from the bus, mentioned above. Code is published in a message" Bidirectional Bus"...


UART with FIFO -> CPLD / FPGA / ?

Started by Martin Maurer in comp.arch.fpga17 years ago 2 replies

Hello, i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps bigger). Can someone tell me, how a FIFO can be...

Hello, i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps bigger). Can someone tell me, how a FIFO can be implemented in hardware ? Is is "simply" an array of bytes, with two counters: one for filling it in and one for reading out ? Or is there a better approach ? At the moment i have only knowledge in ABEL with XILINX CPLD (XC95) series. Is it the right way to...


Basic jitter from a CPLD (XC7500XL)

Started by Jim in comp.arch.fpga17 years ago 15 replies

This is my first design using programmable logic, so apologies if this question can be found in the datasheet or timing report - I don't know...

This is my first design using programmable logic, so apologies if this question can be found in the datasheet or timing report - I don't know quite what I'm looking for. We have a Xilinx XC9572XL (10ns) being driven by either a 12.288MHz or a 6.144MHz clock on the GCK pin. The clock has max jitter 200ps. The CPLD output is a single flip-flop using this clock, driving a 74HC04 gate (for buf...


high input to CPLD

Started by Sonali in comp.arch.fpga15 years ago 5 replies

Hi Friends, I am working on project, where I am using CPLD operating at 5V supply. Can we direcly give the high inut voltage i.e. +5V to its...

Hi Friends, I am working on project, where I am using CPLD operating at 5V supply. Can we direcly give the high inut voltage i.e. +5V to its input pin? Or we have to connect a resistor in between them? If so then how to select a value for +5V supply. simillarly give information for grounding the i/o pin. Regards, Sonali


Looking for FPGA/CPLD skills to develop prototype

Started by Anonymous in comp.arch.fpga13 years ago

I'm looking for an individual with FPGA/CPLD hardware and software skills to develop prototype of a consumer device. Chicago...

I'm looking for an individual with FPGA/CPLD hardware and software skills to develop prototype of a consumer device. Chicago area preferred. cjt101 at yahoo.com