Timing analysis of asynchronous bus peripherals

Started by primiano in comp.arch.fpga11 years ago

Hello everyone, I have a (maybe) simple problem I don't know exactly how to face up. I am given a design (which is made by a third person)...

Hello everyone, I have a (maybe) simple problem I don't know exactly how to face up. I am given a design (which is made by a third person) that realizes simple bus peripherals upon a Altera CPLD. The design is quite simple: the address bus along with the data bus and the READ signals are brought as inputs of the CPLD (outputs are not considered). There is a combinatorial network which, start...


Xilinx CPLD - FSM - one hot - lost token...

Started by Martin Maurer in comp.arch.fpga17 years ago 2 replies

Hello, i am using a FSM in my CPLD design (XC95108). It is written in ABL. It is working fine so far, beside some curious behaviour. On some...

Hello, i am using a FSM in my CPLD design (XC95108). It is written in ABL. It is working fine so far, beside some curious behaviour. On some special condition it seems, my FSM stops working. Something like the token gets lost ??? I have seen it when a lot of "traffic" is on a lot of lines, sometimes already at start up (i still have the xilinx boot adapter connected all the time, when i th...


CPLD Board design newbie questions

Started by Matt Cohen in comp.arch.fpga17 years ago 1 reply

Hi, I've done a bunch of work with FPGAs in courses that I took, but in all those cases I was using either Xilinx's FPGA demoboards or...

Hi, I've done a bunch of work with FPGAs in courses that I took, but in all those cases I was using either Xilinx's FPGA demoboards or an Altera board designed by my university. For my lab now I'm designing a board that will have a Xilinx CPLD on it, and not much else. I'm sort of the token EE in my lab, and having just gotten my bachelor's last year, I've never really designed a board. M...


Programming Xilinx CPLD under linux

Started by James in comp.arch.fpga17 years ago 8 replies

Hi all, I have managed to get the Xilinx command line tools running on linux under wine, however last night while trying to program my device I...

Hi all, I have managed to get the Xilinx command line tools running on linux under wine, however last night while trying to program my device I hit a bit of a wall. After reading the archives of this group, I see that that the iMPACT tool won't run under linux. I have a home made parallel III cable and am trying to program an XC9536 CPLD. How are other people doing this? Thanks so mu...


Bidirectional Bus

Started by nobody in comp.arch.fpga11 years ago 15 replies

After programming an FPGA, XC3S250EVQ100, via Slave Parallel through an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize data and...

After programming an FPGA, XC3S250EVQ100, via Slave Parallel through an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize data and fpga_cclk into the FPGA the done pin goes high. The problem I am having is the bidirectional does not release and allow the FPGA to drive the data bus to CPLD and then finally into an external 8 LED bank. I am fairly confident that the FPGA is loaded...


FPGA and CPLD boards

Started by Tyron in comp.arch.fpga17 years ago

heya ppl i was wondering if any one could help me figure out out to wokr the DI05-CLPD board using the D2-FPGA board the specufication for...

heya ppl i was wondering if any one could help me figure out out to wokr the DI05-CLPD board using the D2-FPGA board the specufication for these boards kind be found at https://digilent.us/Materials/current.html any help would be greatly appreacited.. maybe an example as well.. basically i was try to work with the switches and hte leds on the CPLD board.. Thnx in adv! Tyron


how to evaluate the needed number of gate?

Started by Mouarf in comp.arch.fpga16 years ago 8 replies

hello all, For a hobbyist purpose, I want to drive an LCD display (320x240) with a CPLD or FPGA in a standalone device (weather station)....

hello all, For a hobbyist purpose, I want to drive an LCD display (320x240) with a CPLD or FPGA in a standalone device (weather station). I've already played with FPGA and VHDL for some projects but I was never involved in the hardware part of such projects. The CPLD would have to read data (bitmap picture) from a dual port RAM and write it to the 4 bit data input of the LCD controll...


Spartan 3 configuration

Started by gopal_amlekar in comp.arch.fpga11 years ago 1 reply

Hello, Few days back, I got a good help from this forum about CPLD programming. I have succeded in making my own design based on a...

Hello, Few days back, I got a good help from this forum about CPLD programming. I have succeded in making my own design based on a microcontroller to configure a spartan 2 as well as to program XC95108 CPLD. Now I am moving to Spartan 3 and struggling with it. A very good document from Xilinx about Spartan 2 configuration is XAPP188 (Specifically table 7 on page 11) which lists steps to be ...


Seriell Decoder possibly in ABEL for Lattice CPLD

Started by Timo in comp.arch.fpga18 years ago 1 reply

Hi there I'm not very familar with HDL, but I have to realize a small project with Lattice CPLD. Up to now the most things are working fine,...

Hi there I'm not very familar with HDL, but I have to realize a small project with Lattice CPLD. Up to now the most things are working fine, but now I need help: I'm searching for a device to implement (possibly written in ABEL) to decode signals from PC's seriell port, so I finaly get my eight data bits, under consideration of parity bit. I think, the need for this part is very common, b...


Reliability CPLD/FPGA vs Microcontroller

Started by Falk Salewski in comp.arch.fpga15 years ago 13 replies

I am doing some research on the reliability of microcontrollers software in comparison to hardware description languages for PLDs...

I am doing some research on the reliability of microcontrollers software in comparison to hardware description languages for PLDs (CPLD/FPGA). Another interesting point is whether there are general benefits of one hardware regarding reliability, e.g. in an automotive environment. I read about certification problems if a SRAM based FPGA is programmed every system start and that Flas...


Using part of CPLD to Invert Own Clock

Started by Jim in comp.arch.fpga15 years ago 2 replies

Hi, Apologies upfront if this is a really basic question, as I am rather new to CPLDs. We have a 0-5V squarewave (approx 1MHz, approx 50%...

Hi, Apologies upfront if this is a really basic question, as I am rather new to CPLDs. We have a 0-5V squarewave (approx 1MHz, approx 50% duty) that we wish to use as the clock to a Xilinx CPLD (XC9572XL). We need to select at runtime whether to clock on its rising edge or its falling edge. To achieve this, my current thinking is to run this signal into a spare pin on the Xilinx. A ...


On-Chip Oscillator

Started by Drew in comp.arch.fpga17 years ago 8 replies

Hello Guys, Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I am using Altera Max family parts. I was wondering we can...

Hello Guys, Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I am using Altera Max family parts. I was wondering we can program it using VHDL? Another question I have is, How do I reduce the Rise Time of clock output from CPLD? I need rise time of < 2ns. I need external circuitry but not sure what? Feedback please! Drew


Heating problem of the CPLD

Started by john in comp.arch.fpga15 years ago 7 replies

Hello, I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, my cpld some times work and sometimes does not work at that...

Hello, I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, my cpld some times work and sometimes does not work at that frequency. If I lower the clcok frequency to 12MHz then it always work. bu tin both cases the chip does get hot. I put a heat sink on the chip but if the chip works for long hours then it effects its functionality. Can anybody advice me how to slove this...


XCF02S not seen in the JTAG chain

Started by AugustoEinsfeldt in comp.arch.fpga13 years ago 4 replies

Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now. But like normal days I...

Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now. But like normal days I need to solve this issue asap and thought to ask the list as well. I have a design with a CPLD, a Spartan3 (XC3S400) and a XCF02S memory on the JTAG chain. I cannot see the memory in the JTAG chain, only the CPLD and FPGA. When doing a Get Device ID...


Schematic Entry, Xilinx or Altera?

Started by Parkov in comp.arch.fpga15 years ago 27 replies

Greetings. I'm looking at doing some basic CPLD designs via Schematic Entry. Who has easier to learn/use schematic entry software, Xilinx or...

Greetings. I'm looking at doing some basic CPLD designs via Schematic Entry. Who has easier to learn/use schematic entry software, Xilinx or Altera? Both companies have CPLD's that meet my criteria, and design portability isn't an issue. Thank you.


Replaceme EPROM by CPLD/FPGA

Started by Stef in comp.arch.fpga2 years ago 32 replies

We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in...

We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in the very small available space. A PLCC32 EPROM will not fit unfortunately. Since the memory array is small (256x4 bits), I was thinking this could easily fit into a CPLD or FPGA. But how to program this? The memory is used for calibration data. So...


Maximum system frequency on FPGA/CPLD

Started by Raymond in comp.arch.fpga15 years ago 3 replies

Hi There. Xilinx CPLD XCR3384XL with speed grade -7 have (according to the datasheet) a maximum clock frequency at 135MHz. How have they...

Hi There. Xilinx CPLD XCR3384XL with speed grade -7 have (according to the datasheet) a maximum clock frequency at 135MHz. How have they found that number? I have some timing problems on a FPGA and that trigged my curiousity. (I am assuming that they use a likewise method to find the maximum clock frequency in CPLDs and FPGAs, (but I'm not sure)). Raymond


How to work with global clocks and buffers in CPLD?

Started by Chris Carlen in comp.arch.fpga17 years ago

Hi: I have a Verilog design for a Xilinx XPLA3 CPLD consisting of a toplevel module that instantiates several other modules. I am developing...

Hi: I have a Verilog design for a Xilinx XPLA3 CPLD consisting of a toplevel module that instantiates several other modules. I am developing in WebPACK 5.2i. The current design requires a single clock signal. I am supplying that clock through one of the INn/CLKn inputs of the XPLA3 architecture. Must I do anything special in the Verilog in order to ensure that the clock is route...


data recorder examples?

Started by bob in comp.arch.fpga17 years ago 1 reply

Hi I am new to programmable logic. I got myself a Xilinx CoolRunner II CPLD design kit. I would like to make a project to get into the swing of...

Hi I am new to programmable logic. I got myself a Xilinx CoolRunner II CPLD design kit. I would like to make a project to get into the swing of things. I would like to make a data (Digital Pulse) Recorder. Perhaps it count incoming pulses for a fixed length of time (or set by pc) then store the count and time stamp in the CPLD or FPGA or external memory to later be transferred to the PC ...


Xilinx ISE 6.3 confusion with CPLD logic results

Started by Dave Pollum in comp.arch.fpga15 years ago 2 replies

My VHDL project has out grown a XC95108 CPLD, so I'll be using a XC95144 instead. After running the ISE synthesizer and fitter, all of the...

My VHDL project has out grown a XC95108 CPLD, so I'll be using a XC95144 instead. After running the ISE synthesizer and fitter, all of the XC95144's Function Block Inputs are used. Using exhaustive fit mode, 92% of the function block inputs are used. This still doesn't leave much room for additional features. I then told ISE to use a XC95144XL, instead. Only 64% of the function block input...