Dedicated CLK lines in CPLD

Started by valentin tihomirov in comp.arch.fpga17 years ago 5 replies

I divide primaty CLK1 signal from chip input getting CLK2. CLK2 is submitted to the remaining design. This should consume 2 GCLK (XC9572 CPLD)...

I divide primaty CLK1 signal from chip input getting CLK2. CLK2 is submitted to the remaining design. This should consume 2 GCLK (XC9572 CPLD) lines. However fitter tells me that only 1 of 3 3 GCLK lines used. Design seems to function properly. ChipViewer does not want to show me chip internals.


design optimization

Started by Anonymous in comp.arch.fpga15 years ago 12 replies

Hi, I am targeting the design for XC2C512 coolrunner device. That's the biggest device i could find. Are you aware of any larger CPLD...

Hi, I am targeting the design for XC2C512 coolrunner device. That's the biggest device i could find. Are you aware of any larger CPLD device? I have a dual-edge triggered clock i.e i have no other CPLD choice other than the coolrunner series. I find that i am falling short of a dozen macrocell counts. The fitter report says it needs 524 macrocells and i have 512 macrocells available t...


FPGA/CPLD With Analog Functions?

Started by in comp.arch.fpga17 years ago 7 replies

Hello. I?m new at the FPGA/CPLDs world and I?m currently subscribed to receive Xilinx email communications. I would like to know if is there...

Hello. I?m new at the FPGA/CPLDs world and I?m currently subscribed to receive Xilinx email communications. I would like to know if is there some FPGA/CPLD incorporating some few analog functions or analog blocks like instrumentation amplifiers, OPerational AMPlifiers/(analog amplification), ADCs (Analog-to-Digital-Converter) and DACs? Thank you very much if you are kindly enough to answe


CoolRunner 2 CPLD

Started by Duccio in comp.arch.fpga15 years ago 2 replies

I want to know if the X2c family (coolrunner II) have a non-volatile program memory inside its package: I would like a non-volatile...

I want to know if the X2c family (coolrunner II) have a non-volatile program memory inside its package: I would like a non-volatile memory (eeprom...) that contains the "programs" also when it's extinguished (and with a number of macrocells comparable with a small/medium fpga). However I would know the name of a low-power, non-volatile program memory family (CPLD). Another question: can I u...


RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?

Started by Bruno Cardeira in comp.arch.fpga17 years ago 3 replies

Hello everyone! Can anyone tell me or suggest a way to capture a RC servo PWM signal with a Xilinx CPLD in ABEL?. When the pulse duration is 1ms...

Hello everyone! Can anyone tell me or suggest a way to capture a RC servo PWM signal with a Xilinx CPLD in ABEL?. When the pulse duration is 1ms the digital value is logic 0, when is 2 ms the digital output is a logic 1. Best Regards Thanks in advance


a problem with coolrunner CPLD (XC2C256) GCK0 pin

Started by Arash Majd in comp.arch.fpga15 years ago 12 replies

Hello Dear friends The board we have designed uses of XC2C256 in its center which distributes and switches between different signals in system....

Hello Dear friends The board we have designed uses of XC2C256 in its center which distributes and switches between different signals in system. We use of a timing chip which derives the the output of the optical interface of our board. The output clock of the timing chip (named zl_1944_clk) which is very exact is 19.44 MHz which we have connected to the CPLD's GCK0 input pin and assigned thi...


XPLA3 and Spartan3 Devices Do Not Respond to Programming via Parallel 3 Cable

Started by Mike Hicks in comp.arch.fpga15 years ago

I have a 4 layer, development board in prototype stage. The board has an XCR3128XL CPLD and a Spartan 3 XC3S400 FPGA both running at 3.3 volts....

I have a 4 layer, development board in prototype stage. The board has an XCR3128XL CPLD and a Spartan 3 XC3S400 FPGA both running at 3.3 volts. I started out trying to program the CPLD with a simple clocked counter process in VHDL. I am using a parallel 3 download cable. The code simulates correctly, synthesises and fits, etc and, according the impact software, programs correctly. I can erase...


Unable to scan JTAG chain

Started by mohan in comp.arch.fpga14 years ago 2 replies

I am using max 7000s series cpld.i am using altera byte blaster cable. i am getting error as "unable to scan device chain .cann't scan...

I am using max 7000s series cpld.i am using altera byte blaster cable. i am getting error as "unable to scan device chain .cann't scan jtag chain". what is meaning of this error? what i need to do,to programme CPLD


CPLD 1.8V to 3.3V bidirectional SDA

Started by nobody in comp.arch.fpga3 years ago 10 replies

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and...

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and fsync. Voltage level on the sensor board is 1.8V the PI is 3.3V. I have CPLD hardware that I would like to use to make the bidirectional level shifted SDA as well as level shift the other three. The VHDL behavior is as simple as: begin en


Cyclone 3 Starter Board Question

Started by fpgabuilder in comp.arch.fpga14 years ago 8 replies

Anyone know how the USB Blaster cable loads data to the C3 fpga on the board? The schematic shows a CPLD between the FPGA and the USB...

Anyone know how the USB Blaster cable loads data to the C3 fpga on the board? The schematic shows a CPLD between the FPGA and the USB port. There is a USB to parallel chip between the cpld and the usb port. But I do not see any serial or parallel data going to the fpga. I wish Altera added more details to the starter kit documentation. There is all this source code but it is encrypted. So...


Driving a 30 bit wide LVTTL bus at 160MHz

Started by Dolphin in comp.arch.fpga14 years ago 6 replies

Hello, In my future design I could win a lot of pins if I could drive a bus at 160MHz. Because of bank restrictions and because this bus is...

Hello, In my future design I could win a lot of pins if I could drive a bus at 160MHz. Because of bank restrictions and because this bus is connected to a CPLD, I will have to use LVTTL. Has anybody tried driving a bus in LVTTL at 160MHz? I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has LVDS CPLDs but only the large CPLDs support LVDS inputs. I am afraid that th...


CPLD : Generating reset signal

Started by Valentin Tihomirov in comp.arch.fpga17 years ago 7 replies

Active reset is high. In passive state (nRESET) I pull signal to GND with 130k resistor. Pushing a button connects signal to 3.3vcc with 10R...

Active reset is high. In passive state (nRESET) I pull signal to GND with 130k resistor. Pushing a button connects signal to 3.3vcc with 10R in series. Signal is filtered with 0.1uF capasitor. This circuit works well in the absence of CPLD. After plugging power, signal is low (as expected). Pressing the button activates reset. But RESET signal remains ~2.3v after releasing the button. What...


Where to buy a Xilinx XCR3384XL tq144 CPLD?

Started by Bruno in comp.arch.fpga16 years ago 2 replies

Does anyone know where can I buy a Xilinx XCR3384XL tq144 CPLD? Thanks in advance Best Regards Bruno

Does anyone know where can I buy a Xilinx XCR3384XL tq144 CPLD? Thanks in advance Best Regards Bruno


Xilinx XC9500 CPLD internal pull-up??

Started by Bruno Cardeira in comp.arch.fpga17 years ago 3 replies

Hello! Does anyone know if the Xilinx XC9500 has internal pull-ups (or pull-downs...) when in normal mode (programmable)? If not, how can I...

Hello! Does anyone know if the Xilinx XC9500 has internal pull-ups (or pull-downs...) when in normal mode (programmable)? If not, how can I solve this problem... -> I have a input pin of the CPLD connected to a output pin of a IC that normally is tri-stated. The device gets very hot when the output of the IC is in tri-state (so I think...). Is this possible? how can I solve this without an


Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).

Started by Marcio A. A. Fialho in comp.arch.fpga16 years ago 10 replies

I'm looking for a rad-tolerant, non-volatile (preferably programmable at once) FPGA or CPLD, for a new project (a satellite instrument). After...

I'm looking for a rad-tolerant, non-volatile (preferably programmable at once) FPGA or CPLD, for a new project (a satellite instrument). After searching the Web, I've found out that Actel manufactures micro antifuse FPGAs. These would be fine, but I would like to know if are there any other alternatives besides Actel FPGAs. The device should have around 2500 user gates or more. Reliabi...


lowest-cost FPGA and CPLD

Started by Johnson Liuis in comp.arch.fpga16 years ago 4 replies

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was...

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give me a price range for their lowest-cost solution? I always have an impression that Xilinx provided the lowest-cost chip while Altera provided the high-performance one, is it still true? How is t...


CPLD serial buffer problem

Started by john in comp.arch.fpga15 years ago

Hi, I interfaced a USB 8 bit data bus with a CPLD. I made a 48 bit buffer ( ser_buff ). I am loading the buffer at each falling edge of the...

Hi, I interfaced a USB 8 bit data bus with a CPLD. I made a 48 bit buffer ( ser_buff ). I am loading the buffer at each falling edge of the USB clock. and then copying it into another 48 bit buffer ( Temp ) and the serially ouputting the Temp buffer in another process running on different clock. "inc" signal acts as a trigger signal to the other process to start parallel to serial conversi...


Polmaddie1 - For Traffic Lights Junkies

Started by John Adair in comp.arch.fpga12 years ago 2 replies

As promised another new product Polmaddie1 http://www.enterpoint.co.uk/cpld= _boards/polmaddie1.html. It's a very simple CPLD board based on...

As promised another new product Polmaddie1 http://www.enterpoint.co.uk/cpld= _boards/polmaddie1.html. It's a very simple CPLD board based on Coolrunner-II. It's aimed at doing student or hobby learning with 4 sets of traffic lights to drive and you can even get your PC involved via the serial port providing FTDI FT232RQ chip that's on board. You can write custom software to drive this serial...


Differences between FPGA & CPLD

Started by terry in comp.arch.fpga17 years ago 1 reply

Hi, What are the differences between FPGA & CPLD? Thnaks!

Hi, What are the differences between FPGA & CPLD? Thnaks!


Urgent help with a Simple AND simulation

Started by Peter in comp.arch.fpga12 years ago 3 replies

Hi everyone, I cannot simulate a simple AND Gate the original project: I have downloaded the AND gate VHDL to a CPLD and it works...

Hi everyone, I cannot simulate a simple AND Gate the original project: I have downloaded the AND gate VHDL to a CPLD and it works file without adding extra bits to simulate. You create the ucf file and download to the CPLD and then real time I've tested the out put and it works fine I am getting to the AND gate project becuase I am having problem simulating bigger VHDL code. trying to ...