Intel (Altera) announces Cyclone-10

Started by GaborSzakacs in comp.arch.fpga7 months ago 13 replies

It looks like Intel has learned to count from Microsoft. The previous generation of Cyclone was...

It looks like Intel has learned to count from Microsoft. The previous generation of Cyclone was Cyclone-5. https://www.altera.com/products/fpga/cyclone-series/cyclone-10.html -- Gabor


Why is the Cyclone IV so expensive?

Started by Philipp Klaus Krause in comp.arch.fpga7 years ago 7 replies

A few days ago I had a look at FPGA prices at digikey. Looking at EQFP packages I noticed that at every LE/memory point the Cyclone IV is...

A few days ago I had a look at FPGA prices at digikey. Looking at EQFP packages I noticed that at every LE/memory point the Cyclone IV is about 40% more expensive than the equivalent Cyclone III. Why is the Cyclone IV so much more expensive than the Cyclone III? Philipp


Altera Cyclone 4 deserialization, banks, pll

Started by Serkan Oktem (Alumni) in comp.arch.fpga6 years ago

Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs...

Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data and a clock(120mhz) I need to deserialize 4 bits of data with their respective clocks by Cyclone IV GXEP4CGX150 Questions 1- Which banks should I use for these 30pins (4 bit data and clock inputs) x6 2- W...


Cyclone I & II memory fmax

Started by Martin Schoeberl in comp.arch.fpga11 years ago 6 replies

Hi group, using a 128x32 bit simple dual port memory with independent read and write clock results in following fmax for both clocks (dout is...

Hi group, using a 128x32 bit simple dual port memory with independent read and write clock results in following fmax for both clocks (dout is registered): Cyclone (I) 256 MHz, Cyclone II 210 MHz (restricted) That's a little bit strange. Especially since the fmax for the memories in the data sheet is the other way round: Cyclone (I) 200 MHz and Cyclone II 250 MHz. BTW: according...


WTB FutureElectronics Cyclone NiosII Kit

Started by John Cain in comp.arch.fpga12 years ago

I am looking for a Future Electronics Cyclone NiosII Development Kit with a 1C12 Cyclone FPGA. It was on sale last month for $50 and sold out....

I am looking for a Future Electronics Cyclone NiosII Development Kit with a 1C12 Cyclone FPGA. It was on sale last month for $50 and sold out. Please respond to ppilabs@yahoo.com.


5V FCT TO Cyclone II

Started by majsta in comp.arch.fpga6 years ago 7 replies

Hi there, i just fount this page and i hope that you can help me. Here is what i need to do. I want to interface MC68000 to cyclone II. As...

Hi there, i just fount this page and i hope that you can help me. Here is what i need to do. I want to interface MC68000 to cyclone II. As you allready know MC68000 is 5V system and i need to convert that signals to 3.3V so i can use it in cyclone. I was working with txs0108e and now i know that 5V 3.3V are done in bidirectional mode but i dont know what happened to FCT to LVTTL conversion. Can


Altera Cyclone II and Cyclone III "distributed" RAM?

Started by Ioiod in comp.arch.fpga10 years ago 3 replies

I looked on Altera's website, but I could not find any description on how distributed (LUT-based) RAM works on the CYclone II/III family. FOr...

I looked on Altera's website, but I could not find any description on how distributed (LUT-based) RAM works on the CYclone II/III family. FOr the Stratix III, I see Altera called this feature "M-LAB." Am I missing something obvious? Or do the Cyclone family simply not supported distributed RAM?


Altera, Cyclone III, PCI, LVCMOS, & 3.3V

Started by bob elkind in comp.arch.fpga9 years ago 5 replies

Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? I've read Altera apnote AN447...

Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? I've read Altera apnote AN447 http://www.altera.com/literature/an/an447.pdf I understand this apnote to suggest that any/all 3.3V LVTTL or LVCMOS signals connected to a Cyclone III must employ series termination. (Assumptions for my design: 3.3V VCCIO on the Cyclone III, and the signal...


FPGA's for Ethernet?

Started by Todd in comp.arch.fpga11 years ago 8 replies

Hi all I'm a design engineer trying to evaluate the large number of possibilities for adding Ethernet to our embedded system. So far I've...

Hi all I'm a design engineer trying to evaluate the large number of possibilities for adding Ethernet to our embedded system. So far I've been very impressed by the Altera Cyclone II with NIOS II and free lightweight TCP/IP stack. Adding Ethernet appears to amount to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). Anyone have experience with using the Cyclone II mer...


Synchronous clocking between Cyclone III and SDRAM

Started by jean-francois hasson in comp.arch.fpga8 years ago 11 replies

Hi, We are looking at interfacing the Cyclone III EP3C40 with an SDRAM at 90 MHz. We are considering having the FPGA generate the clock to...

Hi, We are looking at interfacing the Cyclone III EP3C40 with an SDRAM at 90 MHz. We are considering having the FPGA generate the clock to the interface and find a way to ensure both the sdram and the cyclone III are in phase regarding the clock. We could not find up to now a mechanism that would ensure that both the SDRAM and the cyclone III will have their clock almost with the sam...


Cyclone IV announced

Started by Antti in comp.arch.fpga8 years ago 18 replies

Hi Altera is promising 25% more fabric speed than S6 with their new Cyclone IV Antti

Hi Altera is promising 25% more fabric speed than S6 with their new Cyclone IV Antti


1.8V config proms for Cyclone 2s

Started by fpgabuilder in comp.arch.fpga10 years ago

Hi folks, Is it possible to get EPROMs for Altera (Cyclone 2) devices that work at 1.8V? I appreciate the help and...

Hi folks, Is it possible to get EPROMs for Altera (Cyclone 2) devices that work at 1.8V? I appreciate the help and insights. Best, Sanjay


Choose between Cyclone II and Spartan II

Started by Everett in comp.arch.fpga6 years ago 2 replies

Hi All, I am starting a new project for a software defined radio using FPGA. I plan to use simulink and HDL coder with model based design. So...

Hi All, I am starting a new project for a software defined radio using FPGA. I plan to use simulink and HDL coder with model based design. So far I have narrowed down the hardware to cyclone II EP2C70 or Spartan-3A XC3SD3400A. Here is information I have collected: Cost: Cyclone II, board: DE2-70, $329 (education), EP2C70: 256$ or more minimum order of 1 (from Digi-key). Spartan...


mess around with supply voltage to cyclone III

Started by Anonymous in comp.arch.fpga10 years ago 2 replies

Hi, I have a Cyclone III FPGA. I have created a circuit on it whose performance I want to observe under the influence of supply...

Hi, I have a Cyclone III FPGA. I have created a circuit on it whose performance I want to observe under the influence of supply voltage variations and glitches. I want to create intentional glitches of this cyclone iii development board. Any ideas? -PrincessGateArray.


PLL and clock in altera cyclone 2 fpga

Started by Jamie Morken in comp.arch.fpga9 years ago 5 replies

Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to...

Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to this block it will work properly, but the system clock is 27MHz which is too fast for the bit width's of the numerator and denominator even with pipelining selected in lpm_divide. I haven't used the cyclone PLL before, but its lowest output freq...


Cyclone FPGA as Cardbus controller

Started by Marc in comp.arch.fpga13 years ago

Hello, I am thinking about using a Cyclone FPGA as Cardbus controller. With PCI I know that the Cyclone FPGA is working without problems,...

Hello, I am thinking about using a Cyclone FPGA as Cardbus controller. With PCI I know that the Cyclone FPGA is working without problems, but what about the Cardbus specific requirements (or differences to PCI), e.g. power-up current, configuration time, ... Has anybody experiences with it?!??!? Thanks, Marc


Spartan-3A DSP vs. Cyclone III Power-wise

Started by Manny in comp.arch.fpga10 years ago 7 replies

Hi, Well the subject says it all. Just wondering how does Spartan-3A DSP compares to Cyclone III in terms of power efficiency. I know...

Hi, Well the subject says it all. Just wondering how does Spartan-3A DSP compares to Cyclone III in terms of power efficiency. I know the spartan is 90nm and hence should be less favourable. However, does it by any means at least approach the power performance of the cyclone? Thanks, -Manny


Custom timing on Altera Cyclone V GX dev board

Started by Rick C. Hodgin in comp.arch.fpga9 months ago 10 replies

I have a "Cyclone V GX Starter Board," with an Altera Cyclone V GX 5CGXFC5CF27C7N. I've designed a logic layout for a video card that only...

I have a "Cyclone V GX Starter Board," with an Altera Cyclone V GX 5CGXFC5CF27C7N. I've designed a logic layout for a video card that only does SVGA output in graphics modes, and particularly only 1024 x 768 x 75 Hz refresh rate right now. I've developed a custom protocol for using single bytes per pixel, and a palette of 256 colors from a possible range of 4,096 colors. ----- I've g...


Small memories in Cyclone

Started by MikeF in comp.arch.fpga10 years ago 3 replies

Hi I am about to start on a design that will need a number of smallish memories. i.e. 8 deep x 16 wide shift registers, small FIFOs etc. I...

Hi I am about to start on a design that will need a number of smallish memories. i.e. 8 deep x 16 wide shift registers, small FIFOs etc. I am looking at the Spartan 3E and Cyclone II/III. The distributed memories in the Spartan 3E seem like the clincher. Why would I use a Cyclone and either waste a block RAM or quite a few Logic Elements when I can use distributed RAM in the S3E? The Cyc...


Why is Spartan-3 more expensive than Cyclone?

Started by Anonymous in comp.arch.fpga11 years ago 5 replies

Hi everyone, I compared the prices of two FPGAs from Digikey (http://www.digikey.com): +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920,...

Hi everyone, I compared the prices of two FPGAs from Digikey (http://www.digikey.com): +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920, I/O pins:173. Price: 47.87$ +) Altera Cyclone, EP1C6Q240C8N - ND with LC:5980, I/O pins:185. Price: 18.9$ Im relativly new to the FPGA world, but given the larger numbers of LC's and I/O pins that cyclone has, I don't understand why spartan-3 ...