Cyclone V decimation

Started by Piotr Wyderski in comp.arch.fpga2 years ago 14 replies

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing...

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing it on a Cyclone V, resource-wise? My usual approach would be a cascade of CIC decimators followed by a FIR corrector, but since there are the DSP blocks, I don't feel it to be the "right" (albeit correct) approach. I'm new to the V family and lack...


Cyclone Board with // LVDS lines

Started by Keith Williams in comp.arch.fpga16 years ago 1 reply

Hi! I've already googled and dug through several online lists of FPGA boards, but haven't found what I'm looking for, yet. I'm needing a...

Hi! I've already googled and dug through several online lists of FPGA boards, but haven't found what I'm looking for, yet. I'm needing a Cyclone board that has at least 32 LVDS I/O pins available (and terminated). With at least one PLL available to be driven from an external source. Target price of less than $500 U.S. Thanks, Keith


Any chance to buy Cyclone?

Started by Vakaras in comp.arch.fpga18 years ago 3 replies

Hello, Could anybody suggest, where to buy Cyclone devices by Altera in Europe for normal price? (for ex., EP1C3T144Cx) I need just 1-2...

Hello, Could anybody suggest, where to buy Cyclone devices by Altera in Europe for normal price? (for ex., EP1C3T144Cx) I need just 1-2 pieces for testing.. Tryed at Arrow: $50 handling fee they added for international orders (plus $50 for delivering, so $125 for a peace-?....). No any branch of Altera distributors or resellers in my country...:( Any Online catalogs, which ha...


LVDS in cyclone

Started by Eduard Nikke in comp.arch.fpga18 years ago 1 reply

Hi, Can someone help me with this issue. I am looking to build a serialer in a FPGA. Base frequence is 72MHz - 7 bits serialiser - so I...

Hi, Can someone help me with this issue. I am looking to build a serialer in a FPGA. Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of 504MBps. I thought this wat not possible in a Cyclone device but just reads the app. note and it seems to be possible. I have only some strong concerns because there is no timing budget and the IOB are not DDR IOB blocks. ...


Problem with Nios Development Board (Cyclone)

Started by Marcin Olak in comp.arch.fpga16 years ago 3 replies

Hello, I've quickly written AHDL code ( out = !in ), assigned out to the led pin and in to the on-off switch pin. Then I downloaded that...

Hello, I've quickly written AHDL code ( out = !in ), assigned out to the led pin and in to the on-off switch pin. Then I downloaded that code into Cyclone using ByteblasterII. Quartus reported that everything gone fine. BUT... ....all the leds started to blink (including the error led). It seemed like my design was being loaded then configuration controller realized that some...


Implementing PLL in Cyclone - Schematic entry

Started by Len in comp.arch.fpga16 years ago 1 reply

Hi folks, I'm new to the Quartus software. Can someone tell me how to implement a PLL in the schematic entry mode using a Cyclone FPGA? I...

Hi folks, I'm new to the Quartus software. Can someone tell me how to implement a PLL in the schematic entry mode using a Cyclone FPGA? I just want to get started with them, but don't see any "lpm" functions or such to put one in the schematic. Thanks


FPGA's in bulk and pricing

Started by jai....@gmail.com in comp.arch.fpga16 years ago 2 replies

I am posting this again because I don't think my previous one went through, so my apologies if it did and I lost it... I am looking for pricing...

I am posting this again because I don't think my previous one went through, so my apologies if it did and I lost it... I am looking for pricing on Cyclone FPGA's in the 10-20 Quantity range. My usual supplier is Digikey since I'm in Canada, but it costs $50 for a EP1C240 Cyclone, which I think is a lot. What do you guys normally pay for FPGA's, and where can you get them at some volume discou...


timing constraints

Started by ram in comp.arch.fpga14 years ago 1 reply

In the cyclone devices, How to set parameters like tco,tsu,th,tpd.I am not using any M4K RAMS or DSP blocks.I am using for LE_FF timing and...

In the cyclone devices, How to set parameters like tco,tsu,th,tpd.I am not using any M4K RAMS or DSP blocks.I am using for LE_FF timing and LVTTl standards.I am not using fast corner analysis.I have to fix up hold violations of no 96 I referred cyclone II device data sheet DC and timing characteristics page 106-135.How to set this paramters.There are no examples for this.Can you provide exam...


timing constraints

Started by ram in comp.arch.fpga14 years ago

In the cyclone devices, How to set parameters like tco,tsu,th,tpd.I am not using any M4K RAMS or DSP blocks.I am using for LE_FF timing and...

In the cyclone devices, How to set parameters like tco,tsu,th,tpd.I am not using any M4K RAMS or DSP blocks.I am using for LE_FF timing and LVTTL standards.I am not using fast corner analysis.I have to fix up hold violations of no 96 I referred cyclone II device data sheet DC and timing characteristics page 106-135.How to set this paramters.There are no examples for this.Can you provide exam...


anybody ported Jrunner to NIOS I/II??

Started by ron proveniers in comp.arch.fpga17 years ago

On an embedded test-platform we have to configure a remote Altera Cyclone device via its JTAG chain. Our test-platform also has an Altera...

On an embedded test-platform we have to configure a remote Altera Cyclone device via its JTAG chain. Our test-platform also has an Altera Cyclone fpga with a NIOS I SOC. We like to program the remote Cyclone via its JTAG. Right now we think the best method is to port the Altera Jrunner software to the NIOS I. Questions: 1- has anybody done this before (the NIOS port)? 2-what is the max.c...


Cyclone and ByteBlasterMV?

Started by Leon Heller in comp.arch.fpga17 years ago 13 replies

Altera only mentions the ByteBlaster II for programming Cyclone devices. Presumably the ByteBlasterMV doesn't have the right voltage...

Altera only mentions the ByteBlaster II for programming Cyclone devices. Presumably the ByteBlasterMV doesn't have the right voltage thresholds, strictly speaking, but I was wondering if it could be used in a pinch. I made my own from the published schematic (it works fine with Flex10K devices), and would rather avoid having to buy the II, or make my own clone of it. Leon


SRAM on Cyclone Devices

Started by devices in comp.arch.fpga14 years ago 1 reply

Target Device: CYCLONE My project allocates some RAM and initializes it by an Intel Hex File. The Simulator correctly shows the initialized...

Target Device: CYCLONE My project allocates some RAM and initializes it by an Intel Hex File. The Simulator correctly shows the initialized data. lpm_ram_dq ram ( .address (_addr), .q (_dout), .data (_di), .we (_we), .inclock (clk), .outclock (!clk) ); defparam ram.lpm_width = 8; defparam r


A few LatticeMico32 questions

Started by Philip Pemberton in comp.arch.fpga11 years ago 4 replies

Hi, It would seem the Lattice Mico32 support forum has gone dead (no posts/ replies since early February), so I'm asking this here in the hope...

Hi, It would seem the Lattice Mico32 support forum has gone dead (no posts/ replies since early February), so I'm asking this here in the hope there's an lm32 guru somewhere out there... I've (successfully) ported the LatticeMico32 CPU core to the Altera Cyclone II (terASIC DE1 platform, aka Cyclone II FPGA Starter Board). Caching seems to work, as do the WISHBONE interfaces (both of th...


Cyclone 3 Starter Board connector?

Started by Philipp Klaus Krause in comp.arch.fpga14 years ago

The Cyclone 3 Starter Board has this strange "High-Speed Mezzanine Connector (HSMC)". I'd prefer something simpler, such as a 0.1" header. Are...

The Cyclone 3 Starter Board has this strange "High-Speed Mezzanine Connector (HSMC)". I'd prefer something simpler, such as a 0.1" header. Are there any adapters / daughterboards available? Philipp


Code for accessing CF cards on Cyclone dev.board

Started by Jeroen in comp.arch.fpga17 years ago 2 replies

Hi, I'm using a Altera Nios Cyclone dev.board (and the ref-32 design) and I want to use the CF slot for a testapplication. I'm looking for...

Hi, I'm using a Altera Nios Cyclone dev.board (and the ref-32 design) and I want to use the CF slot for a testapplication. I'm looking for some C code to access the CF, so that I won't have to write it myself. Just code to issue IDE commands and get the data from the CF. No filesystem etc. Does someone know where I can find such code? Jeroen


Spartan3E or Cyclone III ?

Started by Sudhir Singh in comp.arch.fpga12 years ago 5 replies

Hi Folks, I am currently in the process for selecting an FPGA for one of my projects. I have always used Xilinx FPGAs but now am considering...

Hi Folks, I am currently in the process for selecting an FPGA for one of my projects. I have always used Xilinx FPGAs but now am considering using Altera. The Altera Cyclone III FPGAs looks like a very cost effective device but I have no idea how well it compares performance wise (will be used for DSP application) to a Spartan3E. I would be very grateful if someone would be able to provide m...


M*Blaze in Cyclone ! End of What? ;)

Started by Antti Lukats in comp.arch.fpga17 years ago 4 replies

Hi I would like to quote Martin Schoeberl: "And a MB on an Altera FPGA, that's the end of the world." Well the end of the world must then...

Hi I would like to quote Martin Schoeberl: "And a MB on an Altera FPGA, that's the end of the world." Well the end of the world must then be TODAY? MB is working in Cyclone FPGA, screenshots available: http://uclinux.openchip.org/forum/viewtopic.php?t=11 some comments - the program that is running in the FPGA is compiled using GPL GNU toolchain so there can be no legal issues with t...


Quick question for an Altera wizard

Started by nospam in comp.arch.fpga14 years ago 4 replies

I have a verilog design on Spartan 3 which needs to move to Cyclone II. The design has 7 128x1 bit asynchronous ROMs using ROM128X1...

I have a verilog design on Spartan 3 which needs to move to Cyclone II. The design has 7 128x1 bit asynchronous ROMs using ROM128X1 primitives (this is called distributed ROM?). Does Cyclone II have something similar? what is the primitive and initialisation syntax? If not will I have to use an lpm_rom megafunction and burn M4K blocks? The ROMs have common addressing so after some...


PCI interface on CYCLONE(ep1c6)

Started by eehinjor in comp.arch.fpga15 years ago 1 reply

Hi,everybody. I have some questions about pci interface on Cyclone.Would someone help me? First,Which pins of PCI should be pull-up or...

Hi,everybody. I have some questions about pci interface on Cyclone.Would someone help me? First,Which pins of PCI should be pull-up or pull-down on the board? Second,Do some resistors(33ohms or 50ohms) to be series between EP1C6 and PCI? Thanks.


Programming and copyright

Started by Nick in comp.arch.fpga16 years ago 29 replies

Hello everybody, I'm developing a software on a Cyclone FPGA. However now we are think about the security of the device : i mean, the code is...

Hello everybody, I'm developing a software on a Cyclone FPGA. However now we are think about the security of the device : i mean, the code is stored on a flash extern to the Cyclone. What can prevent someone from copying the data on this flash and clone the product we are doing ? In Quartus there is a security bit that made me fell confortable, however it works only with a Max device. ...