Alternative To Altera's Cyclone III Starter Board

Started by Abby Brown in comp.arch.fpga10 years ago 4 replies

Hi, Does someone produce a cheaper and simpler substitute for Altera's Cyclone III starter board? It needs to connect to a laptop to...

Hi, Does someone produce a cheaper and simpler substitute for Altera's Cyclone III starter board? It needs to connect to a laptop to download configuration and test cases and upload results (ICT). A driver that connects to Windows .Net would be ideal. Thanks, Gary


Altera Cyclone data is incomplete or messy

Started by Rene Tschaggelar in comp.arch.fpga17 years ago 19 replies

Browsing the 'cyclone device handbook' I spent a great length to find : -the max current for each supply ( VCCIO & VCCINT ) -the expected...

Browsing the 'cyclone device handbook' I spent a great length to find : -the max current for each supply ( VCCIO & VCCINT ) -the expected clocking frequency at the input. I'm aware that 1MHz may not be sufficient to PLL it up to 400MHz or such. to little avail. While I can live with 2 switchmode supplies generating 1.5V and 3.3V at 2A each, and a generic 8pin socket to swap oscillato...


DATA0 pin in Cyclone III device

Started by Hua in comp.arch.fpga13 years ago 1 reply

Hi all, From the datasheet of 3c120 (cyclone III), the data[0] is a pin used in configuration, and in user mode it can be used as a dedicated...

Hi all, From the datasheet of 3c120 (cyclone III), the data[0] is a pin used in configuration, and in user mode it can be used as a dedicated input pin with "optional user control". But when I use it as an input pin in my design, the fitter reports an error saying this pin has been used. Is there any settings I should set before I can use this pin in user mode? Thanks, Hua


Low-cost Altera FPGA roadmap

Started by acd in comp.arch.fpga12 years ago 14 replies

Since the Cyclone III is now 2 years on the market I wonder whether Altera's low-cost line is the Arria branch (with Arria II recently...

Since the Cyclone III is now 2 years on the market I wonder whether Altera's low-cost line is the Arria branch (with Arria II recently announced) or whether there will be Cyclone IV. Since we see the Spartan VI coming from Xilinx this year, one would expect a competing Altera product as well.


Minimalist RS232 on Cyclone

Started by Andrew Steer in comp.arch.fpga18 years ago 4 replies

Hi, I'm new to this newsgroup, and also a relative FPGA newbie (though have lots of hardware and software experince). If I should need the...

Hi, I'm new to this newsgroup, and also a relative FPGA newbie (though have lots of hardware and software experince). If I should need the FAQ, please kindly point me in the right direction. I would like to implement a minimal RS232 interface on my Cyclone device. I only require TxD and RxD signals (I've got an RS232 level- shifter IC on board). I only require a bare-bones implementation...


cyclone's pll

Started by GL in comp.arch.fpga16 years ago 3 replies

Hi all, I'm using a cyclone EP1C6 Q240 and want to instanciate a pll, but using the PLL2 (input are CLK2 and CLK3). My problem is that with...

Hi all, I'm using a cyclone EP1C6 Q240 and want to instanciate a pll, but using the PLL2 (input are CLK2 and CLK3). My problem is that with the design assistant, i can create a macro-function called altpll, but i can't choose the input i want (clk2, on pin 153 of EP1C6Q240 ). how should i do ? regards, -- Ceci est une signature automatique de MesNews. Site : http://www.mesnews....


Cyclone Memory Development Board

Started by ALuPin in comp.arch.fpga17 years ago 1 reply

Hi newsgroup people, does someone know where to find some information about an Altera Cyclone Memory Evaluation Board for DDR SDRAM ? The...

Hi newsgroup people, does someone know where to find some information about an Altera Cyclone Memory Evaluation Board for DDR SDRAM ? The only board I could find is the Lancelot from www.fgpa.nl Are there other boards? Thank you for your help.


Metastability MTBF in Cyclone

Started by Gary Pace in comp.arch.fpga16 years ago 3 replies

Hi All, I have a Cyclone application with a long lifetime and a high realibility requirement (i.e. no subsequent CRC's and retries, the IGBT...

Hi All, I have a Cyclone application with a long lifetime and a high realibility requirement (i.e. no subsequent CRC's and retries, the IGBT just turns on) I am trying to assess the MTBF of metastable events. I have 166MHz clock and 10kHz async. inputs with a single sync. latch. Latencies are best avoided so I'd rather not double sync. unless I have to. The Altera app. note gives an...


Cyclone and NIOS II

Started by GMM50 in comp.arch.fpga16 years ago

Is any using a Cyclone FPGA and NIOS II CPU? Specifically I'm having trouble booting from FLASH. THe boot sequence it to copy FLASH contents...

Is any using a Cyclone FPGA and NIOS II CPU? Specifically I'm having trouble booting from FLASH. THe boot sequence it to copy FLASH contents into DRAM then run out of DRAM. I can load directly into DRAM using the JTAG interface and all is OK. But running freestanding from a power up in NG. Is anyone able to accomplish this? George


Nios - cyclone toolchain questions

Started by tns1 in comp.arch.fpga17 years ago 2 replies

I have downloaded the quartusIIwe, and used it to synthesize some modules for cyclone parts - works great. Now I would like to try SOPC...

I have downloaded the quartusIIwe, and used it to synthesize some modules for cyclone parts - works great. Now I would like to try SOPC builder and compile some C for an existing nios board, but am a little confused about the toolchain. QuartusII comes with cygwin, but it looks like there is no gcc, etc. for nios. Altera's site says the Gnupro tools for nios do not require a license, ...


JTAG issues Cyclone V SoC

Started by Al Clark in comp.arch.fpga7 years ago 3 replies

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog...

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog Devices' SHARC DSPs. I am working on the JTAG connection strategy. It seems to me that separate JTAG connections make more sense than chaining since Quartus may be running separately from the ARM (HPS). Unless someone tells me something diffe...


Cyclone II can't enter in configuration mode with EPCS1.

Started by JaReZ in comp.arch.fpga14 years ago

HI everybody, I am trying to configure a cyclone II with EPCS1 boot loader. the EPCS1 program perfectly with quartus and byteblaster II...

HI everybody, I am trying to configure a cyclone II with EPCS1 boot loader. the EPCS1 program perfectly with quartus and byteblaster II cable. But when at the nstatus pin on the FPGA, it's like it's try to go to VCC during 2 us, then once it's almost reach VCC, it's get down to ground immediatly, and repeat the phenomena again. the FPGA can't leave POR mode. Anybody have an Idea ?...


SDRAM Controller on a cyclone dev kit

Started by Nick in comp.arch.fpga17 years ago 2 replies

Hello, I've been unsuccessfully trying to use the SDRAM on my MJL Cyclone dev kit. I've tried the example (not very well documented) sold with...

Hello, I've been unsuccessfully trying to use the SDRAM on my MJL Cyclone dev kit. I've tried the example (not very well documented) sold with the dev kit, and tried the Altera IP Sdram controller. The way i do it : I connect the sdram controller to the sdram and use a small test module to check it reads and writes. I start with the initialisation sequence of the ram (nop for 100?s then...


Interfacing Cyclone III to 3.3v LVDS devices

Started by liqi...@gmail.com in comp.arch.fpga13 years ago 3 replies

How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks

How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks


Simulating Cyclone II PLL

Started by Mark McDougall in comp.arch.fpga16 years ago 2 replies

Hi, I've got a problem which has me stumped. We've got a design that actually *runs* in real hardware. I'm in the process of adding the...

Hi, I've got a problem which has me stumped. We've got a design that actually *runs* in real hardware. I'm in the process of adding the block to an existing testbench that contains other FPGAs. In the new design (Cyclone II) is a PLL, input frequency 24MHz. I'm generating the clock input in the testbench (VHDL). Two output clocks are used, C1 & C2, both 112MHz (slight phase differ...


Help for Altera Nios II Cyclone EP1C12 evaluation kit!

Started by Jack Zkcmbcyk in comp.arch.fpga15 years ago 2 replies

Hello out there! I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution kit a while ago and didn't get to work with until...

Hello out there! I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution kit a while ago and didn't get to work with until recently. At first I was happy to see how quickly I got the board up and running and interacting with my PC through an Ethernet LAN and serving web pages using the uClinux on-board http server. Having had enough of the demo I started develo...


Is Altera Cyclone a good choice ?

Started by Alessandro Strazzero in comp.arch.fpga16 years ago 15 replies

Dear everybody, the goal of my post is to collect your opinions about the use of Altera Cyclone devices in a rugged environment. I have to...

Dear everybody, the goal of my post is to collect your opinions about the use of Altera Cyclone devices in a rugged environment. I have to design a board which should control a chopper based on GTOs. The environment is a railway vehicle and the following are the conditions I have to consider: - extreme temperature range (-40?C to +85?C) - strong mechanical vibrations - long life duratio...


Altera Cyclone II die revision?

Started by Manfred Balik in comp.arch.fpga14 years ago 1 reply

from the Cyclone II errata sheet: The die revision is identified by the alphanumeric character (Z) before the fab code (first two alphanumeric...

from the Cyclone II errata sheet: The die revision is identified by the alphanumeric character (Z) before the fab code (first two alphanumeric characters) in the date code printed on the top side of the device. A X?Z ## #### ^ Die Revision my EP2C20F484C8N is labeld with (looks a little bit different :-( ): K CAA9T0619A is the die Revision A???? I need this to know, becaus...


Lattice LFEC

Started by Jedi in comp.arch.fpga16 years ago 10 replies

Hello.. Is this normal that same core which performs well for Altera Cyclone device can only run at half speed on a LFEC20-5 device? Tried...

Hello.. Is this normal that same core which performs well for Altera Cyclone device can only run at half speed on a LFEC20-5 device? Tried with several CPU cores from opencores.org and LAttice LFEC20 shows mostly half the performance as Cyclone... rick


add/sub 2:1 mux and ena in a single LE (Cyclone)

Started by Martin Schoeberl in comp.arch.fpga17 years ago 11 replies

I want to realize an add/subtract function, a 2:1 mux between this adder and a load value and an enable of the register in a single LE. As I...

I want to realize an add/subtract function, a 2:1 mux between this adder and a load value and an enable of the register in a single LE. As I can see in the data sheet (Cyclone) this should be possible: There is an extra input addnsub to decide between add and subtract. Two inputs of the LUT are used for the add/sub, the remaining two inputs can perform the 2:1 mux. The register has an additio...