Cyclone III passive serial config issue

Started by Paul Urbanus in comp.arch.fpga13 years ago 1 reply

Hi, my name is Paul, and I'm a long-time Xilinx user. (in your best AA voice, now: "Hi Paul") I'm doing my first Altera design using a Cyclone...

Hi, my name is Paul, and I'm a long-time Xilinx user. (in your best AA voice, now: "Hi Paul") I'm doing my first Altera design using a Cyclone III. The design has a very wide video output bus which drives some ASICs, so the VCCIO voltage is set to 3.0 so the internal series terminations can be used. I believe I understand the interface rules when VCCIO = 3.0V, but now the relationshi...


Decoupling for Altera Cyclone II 2C8

Started by Philip Pemberton in comp.arch.fpga11 years ago 4 replies

Hi guys, I'm designing a PCB for a project of mine (a floppy disc data analyser -- see ). This will be my first project with an FPGA, or at...

Hi guys, I'm designing a PCB for a project of mine (a floppy disc data analyser -- see ). This will be my first project with an FPGA, or at least the first one that's made it as far as actual PCBs being made. I'm using an Altera Cyclone II EP2C8 in TQ144 (144-pin TQFP) package. This has a 40MHz external clock (provided by a TTL oscillator module) which is


Serial communication

Started by Piotr Wyderski in comp.arch.fpga16 years ago

Hello, I have a system composed of a Cyclone device and an 8051-like CPU, which acts as a passive-serial configuration device and later as a...

Hello, I have a system composed of a Cyclone device and an 8051-like CPU, which acts as a passive-serial configuration device and later as a USB2.0 coupler. The FPGA configuration image is clocked to Cyclone using the UART interface (synchronous mode 0, i.e. TXD acts as DCLK and RXD presents one bit at a time to the DATA0 pin). There are also two inverters at these lines: the first one ...


Clock Phase Fun on Cyclone III

Started by Rob Gaddi in comp.arch.fpga10 years ago 1 reply

I've got a project going on a Cyclone III, and have hit an issue that seems like it has a simple solution if only I already knew it. I've got...

I've got a project going on a Cyclone III, and have hit an issue that seems like it has a simple solution if only I already knew it. I've got a 125 MHz input clock (CLK125). I've got an ADC that takes in an LVDS 250 MHz clock (CLKOUT), and outputs 250 Msps parallel LVDS data, changing on the rising edge of a regenerated 250 MHz clock (CLKFB). The phase relationship of my FPGA to anyth...


RS232

Started by ECS.MSc.SOC in comp.arch.fpga10 years ago 1 reply

Hi all I am using Altera DE0 Cyclone III board. I am confused about the RS232 connection in DE0 Cyclone II. my question is that: There...

Hi all I am using Altera DE0 Cyclone III board. I am confused about the RS232 connection in DE0 Cyclone II. my question is that: There are some connection in FPGA board related to the RS232. Dose it mean that there is a transceiver in the DE0 board or I should connect it to a tranceiver? Regards


Memory Handling in Altera Cyclone devices

Started by Vazquez in comp.arch.fpga18 years ago 6 replies

Hello, I am trying to transform a functional behavioral description of a controller module to real hardware in a Cyclone...

Hello, I am trying to transform a functional behavioral description of a controller module to real hardware in a Cyclone device(EP1C6C256C7). The VHDL model of the controller is responsible for the control of the write and read transactions to a data field (two-dimensional array) which could be for example a SRAM block. The problem is that the write- and read- addresses and the -next...


Epp interface with Cyclone

Started by Michele Bergo in comp.arch.fpga16 years ago 4 replies

I want to realize an EPP interface using Altera FPGA Cyclone (read and write operation) but I have some synchronization problems. I want to...

I want to realize an EPP interface using Altera FPGA Cyclone (read and write operation) but I have some synchronization problems. I want to sample datas from a 4 bits chip, storing them in a ZBT SRAM memory (Flow trought) and later acquiring them by parallel port. the chip works at 10MHz but the pll on board can't divide input clock of 20MHz for 2. How can I divide the frequency? thanks. D...


new Lattice FPGAs vs Cyclone and SpartanIII

Started by Paul Sereno in comp.arch.fpga17 years ago 15 replies

I am just wandering if any of you have take a look at the Lattice FPGAs. I do like the DSP functions. is out there any serious comparation...

I am just wandering if any of you have take a look at the Lattice FPGAs. I do like the DSP functions. is out there any serious comparation against SpartanIII and Cyclone? regards, paul


MJL Cyclone Development kit and Quartus II

Started by MarkAren in comp.arch.fpga13 years ago

Hi All, I have a second hand MJL Cyclone Development kit with Altera EP1C20F400C7 FPGA and EPM3064ATC configuration controller. The...

Hi All, I have a second hand MJL Cyclone Development kit with Altera EP1C20F400C7 FPGA and EPM3064ATC configuration controller. The factory supplied FLASH code is GERMS built using NIOS I. I have successfully compiled a test file using Quartus II, V7.2. I have also loaded and run the SRAM Object File (.SOF) file using a USB Byte Blaster using the JTAG interface. I am now trying to con...


Problem with AXI4 Lite in Cyclone V

Started by Anonymous in comp.arch.fpga5 years ago 6 replies

Hi, I have created a simple AXI4-Lite slave, which works perfectly in Xilinx Zynq FPGA. Unfortunately, the same design ported to Altera...

Hi, I have created a simple AXI4-Lite slave, which works perfectly in Xilinx Zynq FPGA. Unfortunately, the same design ported to Altera Cyclone V SoC behaves in a very strange way. The write operations work good. The read operation causes the ARM to hang. Checking the transaction with the Signal Tap I can see, that my core receives ARVALID and responds with data and ARREADY it also receiv...


Cyclone II "altsyncram" timing constraints?

Started by Jules in comp.arch.fpga14 years ago 3 replies

Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module on Cyclone II. I have...

Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module on Cyclone II. I have chapter 8 of the device handbook, which has a basic diagram, but when I try to duplicate the timing of this diagram, I don't seem to be able to get clock speeds above about 100MHz to work correctly (according to Quartus II's simulation). I understood t...


Cyclone II EP2C70 dev kits, where are they?

Started by Tommy Thorn in comp.arch.fpga15 years ago 9 replies

Having just realized that ISE WebPack support ends at an XC3S1500 I set out to locate a Cyclone II EP2C70 based dev kit, but found nothing. I...

Having just realized that ISE WebPack support ends at an XC3S1500 I set out to locate a Cyclone II EP2C70 based dev kit, but found nothing. I thought these parts were launched quite a while ago, what happend? (The XC3S5000 based Zefant DDR looked great until I was reminded of the lack of WebPack support. My budget cannot stretch to the full ISE.) Thanks, Tommy -- fpga (at) numba-tu.c...


LVDS in Cyclone-II

Started by John_H in comp.arch.fpga15 years ago 13 replies

Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't...

Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't true differential drives: an external resistor network is needed to produce proper LVDS levels like in the "old days." Does anyone here have experience with the LVDS drivers? I imagine I'll end up with 0603 resistors rather than a Bourns network...


LVDS output pins of Altera Cyclone II

Started by only...@online.ms in comp.arch.fpga14 years ago 1 reply

Hi, does anybody know how to switch of the LVDS output pins of a Cyclone II? I use the "alt_lvds" megafunction but there are no inputs to...

Hi, does anybody know how to switch of the LVDS output pins of a Cyclone II? I use the "alt_lvds" megafunction but there are no inputs to this megafuction to enable or disable the LVDS output pins. I thought about writing my own serializer as a workaround but I have no idea how this is done. But it should be possible by using the double data rate IOs and some shift registers. T...


Went from Xilinx to Altera: Cyclone-II and I/O pullup?

Started by Xilinx user in comp.arch.fpga14 years ago 2 replies

I'm a longtime Xilinx user, and I've recently switched over to the dark side :) Anyway, I'm new to Quartus-II Web Edition, and I'm trying to...

I'm a longtime Xilinx user, and I've recently switched over to the dark side :) Anyway, I'm new to Quartus-II Web Edition, and I'm trying to port a project from my Xess XSA-3S1000 board to a Altera Cyclone-II Starter Kit. I've run into a problem where I have bidi I/Os which need a PULLUP. The Xilinx Spartan-3's I/Os supported a PULLUP constraint, specified in Xilinx's *.UCF file. I sea...


Embedded Multipliers in Altera Cyclone

Started by dani...@gmail.com in comp.arch.fpga11 years ago 4 replies

Hi all, In my Cyclone 4 based design I'm getting an embedded multiplier inferred, as expected from the following VHDL: C

Hi all, In my Cyclone 4 based design I'm getting an embedded multiplier inferred, as expected from the following VHDL: C


QuartusII Ver11.0 programmer problems?

Started by Nial Stewart in comp.arch.fpga10 years ago 2 replies

I have a client who is trying to use the QuartusII Ver 11.0 stand alone programmer to program a Cyclone IV board, and is having problems and his...

I have a client who is trying to use the QuartusII Ver 11.0 stand alone programmer to program a Cyclone IV board, and is having problems and his machine isn't seeing the programmer (It's an Entner EEBlaster but it also can't see a Terasic blaster so I'm confident that isn't the problem). Version 9.0 of the programmer can see it OK but can't drive the Cyclone IV on his board. Has anyone ...


Cyclone clock

Started by Piotr Wyderski in comp.arch.fpga16 years ago 9 replies

Hello, I have a source of extremely stable and clean clock signal. Its frequency is about 64 MHz. I would like to use it as the main clock...

Hello, I have a source of extremely stable and clean clock signal. Its frequency is about 64 MHz. I would like to use it as the main clock for a Cyclone FPGA chip (1C6, to be exact). The problem is that the signal is a sine wave with the amplitude of about 1Vpp. The exact level is not an issue, I can amplify or attenuate it appropriately, but the shape bothers me: may I feed the FPGA clo...


altera cyclone memory example

Started by Anonymous in comp.arch.fpga15 years ago 7 replies

Hi Everyone, I am a student trying to build a project with Altera's Cyclone FPGA board. For my project, I need to access a large amount of...

Hi Everyone, I am a student trying to build a project with Altera's Cyclone FPGA board. For my project, I need to access a large amount of data, which I would like to store in the board's memory. I did not find any simple example which could show me how to simply read and write to the chip's built-in memory. Is there any ready made interface I could use? I would like not to use the Nios ...


Using an oscillator in a rugged environment

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

Dear everybody, I have to design an ALTERA Cyclone FPGA based board which will be used in a rugged environment in terms of operating...

Dear everybody, I have to design an ALTERA Cyclone FPGA based board which will be used in a rugged environment in terms of operating temperature (-40 to +85 =B0C) and strong EMI interference. I have to provide for the clock to the FPGA and I would like to use a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone internal PLL in order to obtain a 128 MHz clock for the NIOS II ...