Is a gated oscillator using NAND okay within a Cyclone FPGA?

Started by Len in comp.arch.fpga16 years ago 8 replies

Hello, I'm brand new to the world of FPGA's and would like to know if I can implement a gated oscillator using a NAND gate (the output tied...

Hello, I'm brand new to the world of FPGA's and would like to know if I can implement a gated oscillator using a NAND gate (the output tied back to one of the inputs, and the other input as the gate) within my Cyclone I device? Thanks for the newbie help! Len G


Driving Multiple FPGAs and Fanout (Cyclone III)

Started by snowball67 in comp.arch.fpga12 years ago 2 replies

Hi, I have a design that will comprise of 11 FPGA boards: 10 slaves and 1 master and each board is having one cyclone III FPGA. The...

Hi, I have a design that will comprise of 11 FPGA boards: 10 slaves and 1 master and each board is having one cyclone III FPGA. The communication between master and slaves is via a simple SRAM protocol (with addr, data, WR/RD and CS). All boards will be interconnected together on a backplane board, with about 1 inch apart. According to the electrical specifications, the input leakage current...


Relationship between high and low speed clocks

Started by H. Peter Anvin in comp.arch.fpga12 years ago 13 replies

Hello, I have a design which I am porting to a Cyclone II FPGA. This design includes two clocks, one at 25 MHz and one at 100 MHz,...

Hello, I have a design which I am porting to a Cyclone II FPGA. This design includes two clocks, one at 25 MHz and one at 100 MHz, currently generated from the Cyclone II PLL from a common clock (and thus synchronous.) I have avoided it so far, but I'm running into a situation where the high-speed logic would like to understand where it is in relation to the low-speed clock cycle, in ord...


delay in altera cyclone about led

Started by chronoer in comp.arch.fpga15 years ago 5 replies

Dear all i write a simple test for led on altera cyclone board by jtag protocol such as following: led[0] will shine with some...

Dear all i write a simple test for led on altera cyclone board by jtag protocol such as following: led[0] will shine with some frequence reg [31:0] temp_count=0; reg direction=1; parameter delay=23'h600000; always @( posedge clock)begin if(direction==1)begin temp_count=temp_count+1'b1; ...


NIOS II fmax on a Cyclone

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

Dear everybody, I have developed a NIOS II based project which must run on a Cyclone with speed grade 7. The project contains only a NIOS...

Dear everybody, I have developed a NIOS II based project which must run on a Cyclone with speed grade 7. The project contains only a NIOS II/f configuration which includes the following pheriperals: - SRAM interface designed with user custom logic - common flash interface - one interval timer - three uarts - two tightly coupled on-chip memory blocks - one on-chip memo...


Altera NIOS cyclone edition development board problem

Started by Jack in comp.arch.fpga17 years ago 5 replies

hi. i am going through software dev. tutorial that came with nios dev. kt for cyclone and whenever i tried to run insight debugger...

hi. i am going through software dev. tutorial that came with nios dev. kt for cyclone and whenever i tried to run insight debugger with byteblaster II, it always said "failed to connect. here is the command line: nios-debug lcd_demo1.srec # [nios-gdb-server] accepting gdb connection # [nios-gdb-server] connecting to OCI, ocibase 0x00920800 # [nios-gdb-server] ...using byteblaster (altLP...


Questions about clocks on the Cyclone Nios development board

Started by David Brown in comp.arch.fpga17 years ago

I have a Cyclone Nios development board, which I'm using for some test development work. The clocking system on the board seems very strange...

I have a Cyclone Nios development board, which I'm using for some test development work. The clocking system on the board seems very strange to me - I'm wondering if it *is* strange, or if I've just misunderstood things. The board has a 50 MHz oscillator that is used to generate the base clock for the fpga and a signal out to the prototyping cards. That's fair enough. However, there is only...


Altera's counter part to Xilinx's ODDR

Started by Verictor in comp.arch.fpga10 years ago 1 reply

I am moving a design from Xilinx V4 to Altera's Cyclone II. There is an ODDR component in the original design. Can someone point to...

I am moving a design from Xilinx V4 to Altera's Cyclone II. There is an ODDR component in the original design. Can someone point to an equivalent component in Cyclone II? Thanks in advance.


easyfpga is not easy

Started by yp in comp.arch.fpga16 years ago 3 replies

hi, I have brought a cyclone development board (EZ1CUSB-12) from easyfpga (www.easyfpga.com) . The CDROM version is 0.9 There is...

hi, I have brought a cyclone development board (EZ1CUSB-12) from easyfpga (www.easyfpga.com) . The CDROM version is 0.9 There is no documentation/software how to download software to the cyclone chip. According to the web site/menu, it can download from USB ( passive mode) or AS ( active mode, which I think it can download from byteblasterMV cable). Anybody can provide the software code !! ...


Nios2 on Parallax Cyclone board (SmartPack)

Started by Himani in comp.arch.fpga17 years ago

Hi, Has anybody tried running Nios2 Evaluation Version on a Parallax SmartPack (Cyclone) board? Thanks, Himani

Hi, Has anybody tried running Nios2 Evaluation Version on a Parallax SmartPack (Cyclone) board? Thanks, Himani


Cyclone conf flash - 25p10 !

Started by Luis Cupido in comp.arch.fpga16 years ago 19 replies

Hi, I've been using the 25P10 flash to configure cyclone devices, as far as I can see they are exactly equal to the EPCS1 (even silicon ID...

Hi, I've been using the 25P10 flash to configure cyclone devices, as far as I can see they are exactly equal to the EPCS1 (even silicon ID is the same, I suspect it is the same chip inside) All altera devices (in AS) I tested can read it and configure fine, however the Quartus II fail to load data into the 25P10... (I must use another software to load the 25p10 and that is less convenie...


corrupted data when accessing dual port bram in Cyclone II

Started by homoalteraiensis in comp.arch.fpga15 years ago 10 replies

I am having several dual port block rams in a cyclone II device. The access takes place as simple dual port option with only one clock for the...

I am having several dual port block rams in a cyclone II device. The access takes place as simple dual port option with only one clock for the bram but sometimes a write, when a read is done simultaneously. I expexted the old data to appear at the output as demanded, when I defined the brams from within the altera megafunction wizzard. I know about the possible bugs, when using two differen...


Altera HSMC connector

Started by Rick C. Hodgin in comp.arch.fpga5 years ago 18 replies

Hello all. I'm looking for some information about Altera's FPGA. I have this Cyclone V GX dev board: ...

Hello all. I'm looking for some information about Altera's FPGA. I have this Cyclone V GX dev board: https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-start er.html It has a 160-pin HSMC connector, which connects using this flexible cable: https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf http://www.terasic.com.tw/cgi-bin


Cyclone II SSTL-2 on-chip resistors

Started by Sebastien Bourdeauducq in comp.arch.fpga14 years ago 2 replies

Hi, I'm trying to build a board that will use a DDRAM PC2700 memory module connected to a Cyclone II FPGA. It uses SSTL-2 signaling, and...

Hi, I'm trying to build a board that will use a DDRAM PC2700 memory module connected to a Cyclone II FPGA. It uses SSTL-2 signaling, and one thing I really don't understand is why the on-chip series resistor for SSTL-2 seems to be 50 ohms (according to http://www.altera.com/products/devices/cyclone2/features/onchip/cy2-onchip.html) while it should be 25 ohms (according to http://www.inte...


Address Mapping in 4K RAM Blocks in Altera Cyclone Devices

Started by Vazquez in comp.arch.fpga18 years ago 1 reply

Hello, can you tell me if there are application notes available about Address Mapping in 4K RAM Blocks in Altera Cyclone Devices? Thank...

Hello, can you tell me if there are application notes available about Address Mapping in 4K RAM Blocks in Altera Cyclone Devices? Thank you. Kind regards Andres V. G&D System Development


Configuration of Cyclone devices

Started by Nevo in comp.arch.fpga15 years ago

Newbie alert here... I'm trying to design a board that would allow me to configure a Cyclone device either through the JTAG port or by...

Newbie alert here... I'm trying to design a board that would allow me to configure a Cyclone device either through the JTAG port or by downloading configuration data to a serial configuration device. I'm looking at the manual and am trying to reconcile differences between figures 13-9, "In-System Programming of Serial Configuration Devices," and figure 13-19, "JTAG Configuration of a Single...


Driving PLL from general I/O in Altera Cyclone

Started by nfirtaps in comp.arch.fpga14 years ago 9 replies

I am trying to deserialize a DDR signal in my Cyclone. For reasons I won't go into the DDR clock comes in off a general purpose I/O pin. ...

I am trying to deserialize a DDR signal in my Cyclone. For reasons I won't go into the DDR clock comes in off a general purpose I/O pin. I need a way of deserializing this signal, and want to increase the frequency of the DDR clock by 2 so I can use rising edge flip-flops. 1.) Can I somehow drive a PLL with a general purpose I/O 2.) Is there another way of deserializing the DDR signal. ...


Cyclone Dev. Board, how to set lower clk freq?

Started by suomenmaa in comp.arch.fpga16 years ago

I am using Altera's Cyclone EPIC20F4007 Development board and nios I processor The problem is that I am unable to set the clk freq. from 50 Mhz...

I am using Altera's Cyclone EPIC20F4007 Development board and nios I processor The problem is that I am unable to set the clk freq. from 50 Mhz to 2 Mhz and get the board working. I have changed the clk setting in th SOPC to 20 Mhz and also changed the SDRAM_CLK, PLD_CLKOUT and CL settings to 20 MHZ by factor 2/5. I have also tried different phas shift settings for SDRAM_CLK(phase shift is ...


Cyclone on a shared configuration bus

Started by Piotr Wyderski in comp.arch.fpga16 years ago

Hello, is it possible to configure a Cyclone device connected to a shared serial configuration bus using the nCE signal as DCLK enable?...

Hello, is it possible to configure a Cyclone device connected to a shared serial configuration bus using the nCE signal as DCLK enable? I would like to configure it from a SecureDigital card using Passive Serial mode and an external microcontroller responsible for generating DCLK and SD protocol-specific communication with the card. The configuration should be as fast as possible, so I d...


Can Altera Cyclone device's clock input directly used as CLK with PLL?

Started by Binary in comp.arch.fpga15 years ago 3 replies

Hi all, I have a Altera Cyclone chip which is input by a 50MHz osc. I want to use this 50MHz clock directly without PLL. This means I just use...

Hi all, I have a Altera Cyclone chip which is input by a 50MHz osc. I want to use this 50MHz clock directly without PLL. This means I just use a clk as input and assign the PIN GCLK to clk. Is it OK? Thanks in advance. ABAI