Series DCM's and total Lock Time

Started by Anonymous in comp.arch.fpga10 years ago 3 replies

Hi, I googled around a bit but could not find the answer. I am using Xilinx Spartan FPGA, with 2 DCM's in series to generate a 32MHz clock...

Hi, I googled around a bit but could not find the answer. I am using Xilinx Spartan FPGA, with 2 DCM's in series to generate a 32MHz clock (50% duty cycle) from a 75MHz input. (First DCM is divide 2.5, second multiply 32 and divide 30). The first DCM is connected to a system reset via a user pin, and the LOCKED signal of this DCM is used to reset the second DCM. My question : What i...


DCM with instable clock

Started by Anonymous in comp.arch.fpga10 years ago 11 replies
DCM

In a design, I have to generate several clocks with precisely phase relationship, I'd like to use DCM. But the clock_input is not stable. It...

In a design, I have to generate several clocks with precisely phase relationship, I'd like to use DCM. But the clock_input is not stable. It could possiblely change frequency, even stop for a while. I dont have input signal to reset DCM. How can I use DCM in this condition? Or, if don't use DCM, how can I chieve precise phase relationship? Thank you!


DCM ISE6.2.3 sim problem

Started by wolfgang in comp.arch.fpga13 years ago 2 replies

hey guys! i trie to simulate a dcm design with modelsim, but the dcm doesn't start. i tried to reset the dcm after applying clkin, it seems,...

hey guys! i trie to simulate a dcm design with modelsim, but the dcm doesn't start. i tried to reset the dcm after applying clkin, it seems, that the dcm is working, but clkfx is only a amount of spikes instead of a 50:50 clock but at the right frequency. clkin is a 60%:40% clock with 33 MHz. anyone out there with the same problem? thx wolfgang


Error while simulation with XILINX DCM

Started by J?rgen in comp.arch.fpga13 years ago 5 replies

Hi, in order to verify the functionality of XILINX DCM, I have generated a dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module...

Hi, in order to verify the functionality of XILINX DCM, I have generated a dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is embedded into a simple top-level file that only connects the testbench signals (in-clock and reset (=0) to the DCM-module. The DCM reset signal is always set to '0'. Unfortunately, during the simulation with Modelsim, I do not obtain the 4x clock ...


IP unnecessarily using Spartan-3 DCM?

Started by Richard Thompson in comp.arch.fpga12 years ago 9 replies

I've got some Spartan-3 IP from a vendor which uses a DCM. However, the DCM doesn't appear to be doing anything. The DCM is wired up...

I've got some Spartan-3 IP from a vendor which uses a DCM. However, the DCM doesn't appear to be doing anything. The DCM is wired up as follows: 1) A global clock pin on the device drives signal CLK1, which goes into the IP block, where it connects to DCM/CLKIN . CLK1 is not used anywhere else in the design. 2) DCM/CLK0 drives signal CLK2 3) signal CLK2 drives an instantiated BUFG, an...


[VirtexII + DCM + newbie] problems with the clocksignals from DCM

Started by Yttrium in comp.arch.fpga14 years ago 9 replies

hey, i have to use a DCM as i need multiple clocks now the problem is that they should be de-asserted (not active) before some signal, so i need...

hey, i have to use a DCM as i need multiple clocks now the problem is that they should be de-asserted (not active) before some signal, so i need some CE signal. i tried to solve it like this: ddr_clkx2


DCM configuration in Virtex-4 FPGA

Started by Anonymous in comp.arch.fpga9 years ago 4 replies

Hi all, I'm having a little problem to implement a DCM. It's the first time i need it (to be able to use DDR SDRAM). Before i'm going to...

Hi all, I'm having a little problem to implement a DCM. It's the first time i need it (to be able to use DDR SDRAM). Before i'm going to think about a design for a memory controller, i first want to verify that i'm able to control a DCM. I've read a lot of datasheets, and think i know the theory. In ISE 9.2i i added an IP for a DCM which is easy to configure. To test if my configuration is...


CASCADING DCM

Started by vivek in comp.arch.fpga13 years ago 5 replies
DCM

Hi I would like to take the CLK2X output of DCM and give it to the CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result...

Hi I would like to take the CLK2X output of DCM and give it to the CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result in more jitter. regards vivek


Question about Virtex-4 DCM

Started by Anonymous in comp.arch.fpga10 years ago 2 replies

I have an application where I need to model a circuit that has two power rails. A Vitrex-4 has only one internal power rail, so I was thinking...

I have an application where I need to model a circuit that has two power rails. A Vitrex-4 has only one internal power rail, so I was thinking about disabling the DCM to simulate a power-down. This would be done by taking the signal that is normally used to enable power to the rest of the chip, and using it to remove the reset from the DCM. I'm not concerned with DCM weirdness during ...


Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset

Started by John Cappello in comp.arch.fpga13 years ago 7 replies

Hi, We are seeing evidence that a DCM is intermittently selecting the wrong tap position after it completes its lock sequence after a...

Hi, We are seeing evidence that a DCM is intermittently selecting the wrong tap position after it completes its lock sequence after a DCM reset pulse. I'd like to know if anyone has experienced this effect, and if they were able to resolve this problem. In a 2v6000, I am using a variable phase shift DCM which is driven by a 622 MHz clock (divide-by-2 mode). The DCM generates 311 MHz cloc...


Spartan 3 DCM

Started by maxascent in comp.arch.fpga11 years ago 5 replies

If am running a simulation in modelsim an there is a DCM block with a locked signal. Now because correct me if I am wrong but I would need...

If am running a simulation in modelsim an there is a DCM block with a locked signal. Now because correct me if I am wrong but I would need to stimulate the locked signal myself because the DCM will not set it as this is just a simulation and the DCM is a piece of hardware. Hope that makes sense? Thanks Jon


DCM vs. PLL

Started by Rob in comp.arch.fpga11 years ago 13 replies

Serious question: Does Altera's PLL's offer an advantage (veratility, jitter, etc) over Xilinx's DCM's? I'm to understand that the DCM is not...

Serious question: Does Altera's PLL's offer an advantage (veratility, jitter, etc) over Xilinx's DCM's? I'm to understand that the DCM is not a PLL, correct? What is the working principal behind the DCM (any literature links?) This question arises from an upcoming design where we have three serial LVDS interfaces that need to go into a V2PRO part. I implemented this interface with...


DCM lock - require clarification

Started by srini in comp.arch.fpga11 years ago 1 reply

Hi, I am using the VirtexII DCM in my design to generate the master clock for all the modules in my design. The input freq is 20.48 MHz and...

Hi, I am using the VirtexII DCM in my design to generate the master clock for all the modules in my design. The input freq is 20.48 MHz and the output freq from DCM is 61.44 MHz. The "LOCKED" signal from DCM is AND'ed with the system reset and given as reset to all the modules in the design. When I generate the DCM using Coregen, there is a option "wait for DCM lock before DONE signal goes ...


How does the DCM phase shifting circuitry work? Xilinx Spartan 3

Started by Craig Yarbrough in comp.arch.fpga11 years ago 21 replies

Essentially I need to know, for any given DCM configuration, how much the DCM outputs will shift in phase for each time I nail PSINCDEC....

Essentially I need to know, for any given DCM configuration, how much the DCM outputs will shift in phase for each time I nail PSINCDEC. I'm thinking that if I understand better how the PS part of the DCM circuit works I can answer this for myself. I've got a case in with Xilinx but either they're not understanding my question, or they're not sure how to answer, or who knows. Any help would b...


Xilinx Spartan DCM jitter spectrum

Started by Nico Coesel in comp.arch.fpga10 years ago 2 replies

Hello all, Does anyone has some numbers on the frequency spectrum of the jitter from a DCM? The datasheet says the DCM has a jitter of 100ps but...

Hello all, Does anyone has some numbers on the frequency spectrum of the jitter from a DCM? The datasheet says the DCM has a jitter of 100ps but I would like to know a bit more about the spectrum to determine whether or not the clock from a DCM is usefull for sampling. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl


DCM vs PLL

Started by Sharan in comp.arch.fpga8 years ago 8 replies
DCM

Hi, From the datasheets, it is looks like the only major difference between DCM and PLL is that PLL additionally does jitter filtering. Rest...

Hi, From the datasheets, it is looks like the only major difference between DCM and PLL is that PLL additionally does jitter filtering. Rest of the features are present in both these macros. So what decides whether one should use a PLL or DCM in FPGA. The following are the common features present in both DCM and PLL: 1) frequency synth 2) deskew 3) frequency div Additionally DCM can...


DCM CLK driving load problem

Started by ekav...@gmail.com in comp.arch.fpga10 years ago 1 reply

hi , i have a probelm while i am using the DCM for clock mutiply. i am using single DCM for my virtex 2 pro device. i have two sub...

hi , i have a probelm while i am using the DCM for clock mutiply. i am using single DCM for my virtex 2 pro device. i have two sub modules and a top module. i need to use DCM in all the 3 modules (2 sub modules and top module). so i invoked dcm and component instantiation in all the 3 modules. but i am facing the problem while i am mapping . its throwing the error... like error: ERROR:L...


Problem locking a DCM driven by FX output of another DCM

Started by MM in comp.arch.fpga10 years ago 16 replies
DCM

I have a design with 3 DCMs. The first DCM generates 280 MHz out of 210 MHz. It is then divided by 2 and 4 in a PMCD. There are 2 more DCMs, one...

I have a design with 3 DCMs. The first DCM generates 280 MHz out of 210 MHz. It is then divided by 2 and 4 in a PMCD. There are 2 more DCMs, one driven by resulting 70 MHz clock and another by 140 MHz clock. Both have problem locking. Their resets are slightly delayed and negated locked condition of the first DCM. As it stands now I need to reset the first DCM a few times until I get all...


Simulation of DCM with Xilinx 8.2 and Modelsim 6.1

Started by Frai in comp.arch.fpga10 years ago

Hello, for some reason I still don't understand, when I simulate my Post Place & Route model, the DCM that was configured to introduce a delay...

Hello, for some reason I still don't understand, when I simulate my Post Place & Route model, the DCM that was configured to introduce a delay of 2ns does not work properly. It shows a delay of 1.3 ns instead. This is the code that I use to instantiate the DCM: -- DCM with fixed positive phase shift (2 ns, configured with Coregen) Inst_my_dcm_a: my_dcm PORT MAP( CLKIN_IN => dsp_clk_p


DCM LOCKED as reset

Started by Anonymous in comp.arch.fpga12 years ago 3 replies
DCM

Hi, Can DCM's LOCKED o/p signal be used as reset within FPGA? is this scheme feasible :- PowerON Reset acts as DCM reset. DCM's "Locked"...

Hi, Can DCM's LOCKED o/p signal be used as reset within FPGA? is this scheme feasible :- PowerON Reset acts as DCM reset. DCM's "Locked" signal, shifted by 1 SRL16 acts as reset for all the functionality (say FSMs) within FPGA. *FSM has active low reset The possible need for this scheme: When PowerON reset connected to DCM reset gets De-asserted, DCM starts "loking" the clock. At the...