Altera DSP Builder

Started by DC in comp.arch.fpga11 years ago

Hi guys, Seems like Altera's DSP Builder has undergo a lot of improvements over the past year or so. Trying to connect with other DSP...

Hi guys, Seems like Altera's DSP Builder has undergo a lot of improvements over the past year or so. Trying to connect with other DSP Builder aficionados and to promote more discussion on DSP Builder in general, I have created a google group altera_dspbuilder. There, we can help each other out with: - DSP Builder designs - DSP Builder how-tos - Understanding Altera's DSP related IP cor...


Can the complex DSP archetecture based on FPGA+DSP be replaced by FPGA

Started by zhj1985 in comp.arch.fpga8 years ago 6 replies

Generally, the most popular DSP archetecture which focused on complex digital signal processing is based on DSP +FPGA. FPGA is often used as...

Generally, the most popular DSP archetecture which focused on complex digital signal processing is based on DSP +FPGA. FPGA is often used as a coprocessor for a DSP because those PowerPC 440 cores aren't as fast as DSP and those algorithms which are developed by C language can be developped more easily than those developed by Verilog or VHDL language. However, as the time goes, FPGA has develop...


A Way for a DSP to tell an FPGA to load itself from Flash

Started by axr0284 in comp.arch.fpga10 years ago 5 replies

Hi, my setup is as follows: 1) DSP ADSP-21065L 2) Xilinx xc3s250 3) Intel JS2BF320J3D Flash I am able to have the DSP load itself from...

Hi, my setup is as follows: 1) DSP ADSP-21065L 2) Xilinx xc3s250 3) Intel JS2BF320J3D Flash I am able to have the DSP load itself from flash but after it's done loading, I would like the DSP to tell the FPGA to load itself from the same flash. They will be sharing address and data lines and cannot operate at the same time. I am wondering if there is a way for the DSP to tell the FPGA...


TI DSP soft core in Xilinx?

Started by cpope in comp.arch.fpga10 years ago 5 replies

I have a V4FX based product and I'd like to have a DSP coprocessor to go with the the powerpc that handles my operating system. Are there TI c54x...

I have a V4FX based product and I'd like to have a DSP coprocessor to go with the the powerpc that handles my operating system. Are there TI c54x or c3x soft cores out there that could be compiled into a xilinx fpga? Could be anyone's dsp, I suppose, so long as it has a large existing code base and mature tools. Also is microblaze an option? Can it do significant DSP? Thanks, Clark ...


Spartan3 initialization with DSP

Started by Marco in comp.arch.fpga12 years ago 6 replies
DSP

Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking to connect the CCLK and DIN pins to the serial port of the DSP...

Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking to connect the CCLK and DIN pins to the serial port of the DSP (SPORT), but while the DIN is dual-purpose, the CCLK is dedicated. I'll then need, when all properly configured, FPGA and DSP to communicate with the SPORT once again for the normal work of the board. Here comes the issue because the CCLK used for the initiali...


Xilinx Spartan 3A/DSP with Coregen 9.2i?

Started by talkb in comp.arch.fpga10 years ago

I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.) When I ran Core Generator 9.2i.04 (with IP Update #2), created a...

I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.) When I ran Core Generator 9.2i.04 (with IP Update #2), created a new Spartan3A/DSP project, then looked at what wonderous DSP-blocks I could add, I discovered almost everything fun is greyed out. Basically, the IP-Cores haven't been updated to support the 3A-DSP family (only the regular Spartan 3, 3E, 3A/3AN.) Well...


Mistake in Xilinx dsp-book.pdf?

Started by Holger Blum in comp.arch.fpga12 years ago 3 replies

Hello! While working with a MAC-FIR I came across an equation in Xilinx' DSP-book...

Hello! While working with a MAC-FIR I came across an equation in Xilinx' DSP-book (http://www.xilinx.com/publications/books/dsp/dsp-book.pdf) which seems to be wrong in my eyes. On page 65 equation 4.4 for the generic saturation level says Output width = ceil(log2(2^(b-1)*2^(c-1)*N))+1 Where b/c are the numbers of data/coefficient bits and N is the filter length. This formula is, apa...


Altera DDR SDRAM & external DSP

Started by Jerry in comp.arch.fpga13 years ago

The question is "Has anyone successfully integrated two DDR SDRAM controllers controlling one block of ram?" The alternate approach is to use...

The question is "Has anyone successfully integrated two DDR SDRAM controllers controlling one block of ram?" The alternate approach is to use the DSP HPI port as the transfer port between the shared SDRAM and the DSP. This would not rely on using the DSP DDR SDRAM controller to access the shared ram. The bandwidth takes a hit but the overall system preformance is not affected. Oh the inte...


1.8V LVDS on spartan3A DSP

Started by Guru in comp.arch.fpga8 years ago 4 replies

Hello everybody, I am developing a camera with a Spartan3A DSP and a sensor which uses 1.8V LVDS. The Spartan 3A DSP datasheet says that only...

Hello everybody, I am developing a camera with a Spartan3A DSP and a sensor which uses 1.8V LVDS. The Spartan 3A DSP datasheet says that only 2.5 and 3.3V LVDS is supported. The signal rate is 108MHz DDR. Any suggestions what should I do? Specify in UCF LVDS_25 and pray to work OK? It is pretty much the same with a Spartan6. Best regards, Ales


Newbie looking for guidance

Started by ever...@gmail.com in comp.arch.fpga10 years ago 10 replies

Good Afternoon- I posted this to comp.dsp the other day but had someone suggest I post it here. I'm interested in learning more about...

Good Afternoon- I posted this to comp.dsp the other day but had someone suggest I post it here. I'm interested in learning more about DSP's and actually getting my feet wet with DSP hardware. I have three primary interests: 1) robotics 2) computer vision 3) software defined radios. My original intent was to keep working with Atmel AVR's in robotics and not learn more about FPGA...


DSP soft processors

Started by Anonymous in comp.arch.fpga12 years ago 4 replies
DSP

Hi folks, are there any DSP soft processor cores for fpgas available. I have done a search and only found 32 bit RISCs but no DSP processor...

Hi folks, are there any DSP soft processor cores for fpgas available. I have done a search and only found 32 bit RISCs but no DSP processor cores. Thanks in advance Sudhir


DSP

Started by SaHiD in comp.arch.fpga12 years ago 1 reply
DSP

Please Give me outline of doing a project of dsp processor design.

Please Give me outline of doing a project of dsp processor design.


Virtex 5 DSP.

Started by Anonymous in comp.arch.fpga9 years ago 5 replies

Hi, Im new to DSP stuff and have a very simple question. Since the multiplier in virtex 5 dsp is 2's complement ... does that mean when using...

Hi, Im new to DSP stuff and have a very simple question. Since the multiplier in virtex 5 dsp is 2's complement ... does that mean when using the std_logic_unsigned library, the maximum number of bits A input can have is 24 instead of 25 and 17 instead of 18 for B input? Whereas I can use 25 bits for A and 18 for B by using the std_logic_signed library? thanks.


FPGA/DSP system design problem

Started by Anonymous in comp.arch.fpga8 years ago 3 replies

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > DPRAM 2. ADC -> FPGA, this m


Stratix DSP Block: Choosing which FFs are enabled

Started by Rajeev in comp.arch.fpga13 years ago 2 replies

I'm trying to increase the speed of my Stratix design and would like to change which FFs are turned on within a DSP block. The Stratix...

I'm trying to increase the speed of my Stratix design and would like to change which FFs are turned on within a DSP block. The Stratix handbook shows the DSP path something like this: [ FF ] [ X ] [ FF ] [ + ] [ FF ] where [X] is the multiplier block, [+] is an accumulate block and all registers are optional. I don't use any of the accumulators, and I use pipeline_delay=2 going throu...


DSP with sensor i2c interface

Started by Gladys in comp.arch.fpga7 years ago 3 replies
DSP

Hi all, I have to interface DSP with 3 image sensor,s there're only two i2c GPIO for DSP, so I need to implement an i2c core in FPGA,...

Hi all, I have to interface DSP with 3 image sensor,s there're only two i2c GPIO for DSP, so I need to implement an i2c core in FPGA, I've implemented an i2c slave core to receive data from DSP and store them with a large LUT in my FPGA and another i2c master core in FPGA to send the stored i2c data to the 3 sensors, Now I'm wondering if I can use FPGA as an arbitration core, what the FPG...


how to choose the FPGA/DSP coprocessor system architecture

Started by Anonymous in comp.arch.fpga8 years ago 1 reply

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > DPRAM 2. ADC -> FPGA, this mea


max lvds IO speed on V2Pro

Started by sjulhes in comp.arch.fpga11 years ago 1 reply

Hi, We have to interface a V2Pro with a DSP's communication ports which have LVDS links up to 500Mhz ( taken from datasheet ). We have some...

Hi, We have to interface a V2Pro with a DSP's communication ports which have LVDS links up to 500Mhz ( taken from datasheet ). We have some experience on V2Pro LVDS I/O but at slow speed and we are wondering what speed we will be able to reach with this LVDS DSP link. DSP and FPGA are on the same board at a reasonnable distance ( something like 10-15 cm ). Does someone has a feedbac...


Architecture of FPGA

Started by Anonymous in comp.arch.fpga8 years ago 11 replies
DSP

Dear all, I am very interested in the arcchitecture of FPGA of commercial product. But I have the following questions: 1. Is that all logic...

Dear all, I am very interested in the arcchitecture of FPGA of commercial product. But I have the following questions: 1. Is that all logic elements in FPGA are rectangular in shape (e.g. CLB) and why ? 2. Why DSP/ Memory are arranged in column rather than putting together? 3. Why DSP and Memory are rectangular in shape ? 4. Are there special wire connection between DSP or memory ? e.g. bu...


TI DSP + Virtex-5 using EMIF interface

Started by techG in comp.arch.fpga9 years ago 2 replies

Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are very time consuming and...

Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are very time consuming and an hardware parallel solution can help to satisfy time constraints. Finally I decided for a mixed SW and HW that consists in a TI DSP and a Virtex-5 connected togheter on EMIF. Initially I choosed a Virtex-5SX, because it has a large number of DSP ...