did i miss edk 9.2

Started by u_st...@yahoo.de in comp.arch.fpga10 years ago 5 replies

hi just i quick question: did i miss edk 9.2? there are some service packs for edk 9.2 on the xilinx web site but i can't find edk 9.2 itself...

hi just i quick question: did i miss edk 9.2? there are some service packs for edk 9.2 on the xilinx web site but i can't find edk 9.2 itself on the webpage... it still says edk 9.1. i'm i missing something? thanks


Xilinx EDK on Linux

Started by Simon in comp.arch.fpga13 years ago

Hi folks, two things about the EDK on Linux: 1) If I have paid for BaseX 6.3i (and received an upgrade to 7.1i), and also paid for the EDK...

Hi folks, two things about the EDK on Linux: 1) If I have paid for BaseX 6.3i (and received an upgrade to 7.1i), and also paid for the EDK 6.3, is there an upgrade path for the EDK as well ? I've only just bought the EDK, do I have to buy it again, or is it under the same upgrade conditions as ISE ? Or is it just not ready yet ? 2) I think I've found a bug in the EDK's X interface - if...


Update EDK 6.1 to EDK 6.3

Started by Linas Petras in comp.arch.fpga13 years ago 1 reply

Can anyone tell me if it is possible to update from Xilinx EDK 6.1.xx to EDK 6.3.xx. It appears that I need to buy a new copy of the EDK to be...

Can anyone tell me if it is possible to update from Xilinx EDK 6.1.xx to EDK 6.3.xx. It appears that I need to buy a new copy of the EDK to be able to update from EDK 6.1 Linas


EDK post 7.1 Opinions

Started by motty in comp.arch.fpga11 years ago

I was just wondering what others thought about the 'New 8.X' EDK. Three people in my group at work have used the EDK since 6.1 and we are all a...

I was just wondering what others thought about the 'New 8.X' EDK. Three people in my group at work have used the EDK since 6.1 and we are all a little disappointed with the newest EDK's. It's functionality is the same, but the GUI and interfaces are all apparently totally different. There are things that we got used to using in the older versions that are different here (ex. core version pu...


Xilinx Christmas present: EDK 6.3 !

Started by Antti Lukats in comp.arch.fpga13 years ago 2 replies

Hi all, Christmas is closing so everybody is making presents. So is Xilinx. I just got mine! Read the story...

Hi all, Christmas is closing so everybody is making presents. So is Xilinx. I just got mine! Read the story below: *********************************************************************** ISE/EDK/ChipScope update to 6.3 In attempt to get our EDK based SoC systems up and running again in EDK 6.3 I ended up creating simplest possible SoC using BSB (because none of working EDK 6.2 projects ...


EDK and SYSGEN

Started by Fizzy in comp.arch.fpga12 years ago 3 replies

Any buddy know how the following can be done. I need to connect the model developed in sysgen to EDK desgin. The EDK design has PowerPC405 so...

Any buddy know how the following can be done. I need to connect the model developed in sysgen to EDK desgin. The EDK design has PowerPC405 so EDK Pcore block in Sysgen is useless as it only supports FSL for microblaze... Any suggestion how it can be done... Only objective is to integrate some model developed to PLB bus in EDK as user core


Upgrading from EDK 8.1 to EDK 9.1i

Started by Anonymous in comp.arch.fpga10 years ago 2 replies

Gang I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a copy of the the EDK 8.1 and uses ISE 8.1 Webpack. I would like...

Gang I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a copy of the the EDK 8.1 and uses ISE 8.1 Webpack. I would like to load the EDK 9.1 and ISE 9.1 Webpack on my machine. I am running Windows XP with SP2, 2gb of RAM and have 200gb of free hard disk space. 1. Can the version 8 executables coexist with the version 9 executes? 2. Do I have to purchase the 9.1 EDK?...


EDK and multipleprocessors - Virtex2p

Started by Anonymous in comp.arch.fpga11 years ago
EDK

Has anyone successfully configured the two PowerPCs inside XUP2VP (virtex2Pro) using EDK?...as I know there are no features in EDK to configure...

Has anyone successfully configured the two PowerPCs inside XUP2VP (virtex2Pro) using EDK?...as I know there are no features in EDK to configure both the PowerPCs. Wondering is any other way of configuring both PowerPCs using EDK....


EDK oddity

Started by MS in comp.arch.fpga14 years ago

So I have a Memec P7 evaluation board with the EDK and a Parallel 4 download cable. We are doing something very basic here to just get our feet...

So I have a Memec P7 evaluation board with the EDK and a Parallel 4 download cable. We are doing something very basic here to just get our feet wet. All we are doing is writing to the UART a simple hello world program. We wrote some C code, and then stepped through the base system builder using this board. We went thru all the steps in the EDK and downloaded right from the EDK to the bo...


How to get Synplify 7,0 Pro and Xilinx EDK 3,2 work together.

Started by Martin Ericson in comp.arch.fpga14 years ago 1 reply

Hi! I have just uppgraded to Xilinx EDK 3,2 and now i cant choose to synthesise with Synplify in "project options -> hierarchy and flow....

Hi! I have just uppgraded to Xilinx EDK 3,2 and now i cant choose to synthesise with Synplify in "project options -> hierarchy and flow. It worked with EDK 3,1 but not in EDK 3,2. Do you have any sugestions what seems to be the problem. Please advice. Martin Ericson Halmstad Univercity Sweden


EDK 8.2i/cygwin issues

Started by Peter Mendham in comp.arch.fpga11 years ago 4 replies

Dear all, I am new to the EDK and just trying out my first project. I am running EDK 8.2i on Windows XP . I already have an install of...

Dear all, I am new to the EDK and just trying out my first project. I am running EDK 8.2i on Windows XP . I already have an install of cygwin and would prefer to use that rather than the one bundled with the EDK. If I do Hardware-> Generate Netlist I get a parse error on the makefile, caused by the line XILINX_EDK_DIR = C:/EDK_82 in system_incl.make. The standard cygwin version of


Upgrading the EDK from 6.3

Started by Simon in comp.arch.fpga12 years ago 4 replies

So, having had something of a forced absence from FPGA's for a few months, I've just been looking at upgrading to 7.1 for both ISE and EDK. My...

So, having had something of a forced absence from FPGA's for a few months, I've just been looking at upgrading to 7.1 for both ISE and EDK. My BaseX subscription seems to have allowed me to update ISE to 7.1, but I can't see any way of upgrading my EDK ? Questions: 1) Is it possible to do an upgrade, or is it a question of re-purchasing the EDK every time there's a release ? I bought...


EDK Simulation on NCSIM

Started by motty in comp.arch.fpga11 years ago 1 reply

Does anyone have a good recipe for simulating an EDK project in NC- Sim? I am looking at the NC Launch (GUI front end) revision and it...

Does anyone have a good recipe for simulating an EDK project in NC- Sim? I am looking at the NC Launch (GUI front end) revision and it is 05.40-s015. I am using EDK 8.2 with the latest service pack. I have done this in the past, but abandoned it b/c I couldn't simulate any useful amount of time before the thing blew up. I would think that a moderately populated EDK would sim OK. Hell, N...


Old EDK versions

Started by Alexey in comp.arch.fpga8 years ago 1 reply
EDK

Hi, I have an old project that was designed in EDK 7.1. Is there anywhere I can download old versions of EDK; the new one , EDK 11, failed...

Hi, I have an old project that was designed in EDK 7.1. Is there anywhere I can download old versions of EDK; the new one , EDK 11, failed to open the project stating incompatible cores.


ED 9.2 too new cygwin error

Started by Antti in comp.arch.fpga9 years ago 7 replies

I just wanted to make a smalll change so launched EDK 9.2 (poroject was done with 9.2) but no luck EDK happily report it FOUND cygwin (why...

I just wanted to make a smalll change so launched EDK 9.2 (poroject was done with 9.2) but no luck EDK happily report it FOUND cygwin (why should it say that? I dont wannt know it, as i want EDK not cygwin!) when i tried to build the project it says CAN NOT USE cygwin NEWER than 1.24 !? does it really mean taht EACH EDK/ISE version has ot be canned into special VM virutal machine wi...


Install two version of EDK/ISE (8.1, 8.2) in my windows xp?

Started by Pablo in comp.arch.fpga10 years ago 5 replies

Is it possible to install two diferent versions of EDK/ISE, that is, one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the first...

Is it possible to install two diferent versions of EDK/ISE, that is, one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the first one for simulink, but my custom board uses the second one (for the drivers). I suppose that the problem is the "Path Variable". Has anyone some experience in this?. I will post my results as soon as possible. Regards, Pablo


downto usage in EDK

Started by Manny in comp.arch.fpga11 years ago 3 replies

Hi, I vaguely seem to remember a provision on the use of downto in EDK. I tried to dig this out before posting this with no...

Hi, I vaguely seem to remember a provision on the use of downto in EDK. I tried to dig this out before posting this with no luck---Can't remember where I came across this though I tried a couple of keyword searches in random EDK pdf docs. Kinda doubtful about something I've just written in EDK using many downto's. Would appreciate a hint on this. BTW, is Xilinx planning any short-term r...


Synthesis with EDK 6.3

Started by Marco in comp.arch.fpga13 years ago

Hallo, I have tried to export an edk project to ise, but before exporting, edk make synthesis with xst. Into the project option I have chosen...

Hallo, I have tried to export an edk project to ise, but before exporting, edk make synthesis with xst. Into the project option I have chosen Synthesis tool: none. Why edk make synthesis in any case? I would make synthesis of the edk project with synplify. Marco


EDK: DCR bus doesn't work

Started by MM in comp.arch.fpga12 years ago 1 reply

Dear EDK experts, Here I am again with an EDK problem... I have a top level ISE design and an EDK submodule (PPC). I am trying to bring a DCR...

Dear EDK experts, Here I am again with an EDK problem... I have a top level ISE design and an EDK submodule (PPC). I am trying to bring a DCR bus out from the EDK submodule into the top level ISE design. Since I want this bus to be in the normal address space I added the opb2dcr_bridge to my design. I assigned the DCR master side of bridge to the external ports of the EDK submodule. All of ...


[EDK tool] simulation setup

Started by Pasacco in comp.arch.fpga10 years ago 1 reply

Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following...

Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following steps: ------------------------------------------- In order to compile COMPXLIB, I used the EDK simulation library compilation wizard Project -> Project options -> HDL and Simulation -> Simulation library path EDK library = C:/EDK/EDK_LIB Xilinx library = C:/Xilinx/Xilinx_LIB ----