high bandwitch ethernet communication

Started by eliben in comp.arch.fpga14 years ago 30 replies

Hello, In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and send all the data...

Hello, In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and send all the data over Gigabit Ethernet. The bandwidth is ~60 MByte/s, sustained. While generally sending this amount of data is possible over Gbit Ethernet, doing so in an embedded system isn't easy. That's because we need to send it by UDP or TCP, for which a TCP/UDP/IP...


Ethernet Encoding scheme

Started by Anonymous in comp.arch.fpga16 years ago 6 replies

Hi All, I want some guidence for encoding schemes used in ethernet I know that for gigabit ethernet mostly the 8b10b encoding scheme...

Hi All, I want some guidence for encoding schemes used in ethernet I know that for gigabit ethernet mostly the 8b10b encoding scheme is used and also I have heard about 64b/66b scheme. which one is actually used....? If I need to send my data on ethernet which one I should use and while receiving any data, is there any method for detecting that the receiving data is coded in which ...


Old XCV50 FPGA and Ethernet

Started by quantum in comp.arch.fpga17 years ago 1 reply

Hi, I am the proud new owner of a Virtex XCV50 sitting on a XESS protoboard. I know this is an old system but I want to learn about FPGA's...

Hi, I am the proud new owner of a Virtex XCV50 sitting on a XESS protoboard. I know this is an old system but I want to learn about FPGA's and VHDL with it. Does anyone have a program that I can use to make the Ethernet interface work or perhaps the video inputs. I prefer to have some TCP/IP software so I can connect it to a network and test the ethernet. Any pointers are greatly ...


FPGA board with multiple Ethernet connections (Gigabit Ethernet)

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

Hi, (this is my second attempt to get some help on the subject). I am searching for an FPGA board having multiple gigabit ethernet connectivity...

Hi, (this is my second attempt to get some help on the subject). I am searching for an FPGA board having multiple gigabit ethernet connectivity support on it. To be more precise, I need to have multiple RJ45 connectors and associated logic (PHYs) on the FPGA board so that I can process multiple ethernet streams on the FPGA. Can anyone suggest any such board? or any add-on module which can be ...


Ethernet & FPGA

Started by Stefan Kopetsch in comp.arch.fpga17 years ago 2 replies

Hi... i'll write my bachelor thesis about the implementation of ethernet and possible tcp/ip layers in an fpga. does someone have experience...

Hi... i'll write my bachelor thesis about the implementation of ethernet and possible tcp/ip layers in an fpga. does someone have experience doing it? especially using open source ip cores like the ethernet MAC core from opencores.org? would be nice if someone could share their experience. another point is the implementation of tcp/ip. does it make sense to do it all in hardware or is...


Help required on Ethernet with FPGA

Started by renupriya in comp.arch.fpga12 years ago 1 reply

Hi .. I'm working on a project which involves a design that has NiOS II processor, DDRSDRAM, SSRAM, a custom Ethernet MAC and other...

Hi .. I'm working on a project which involves a design that has NiOS II processor, DDRSDRAM, SSRAM, a custom Ethernet MAC and other components and I've to run an application on it.. I use NiOS II embedded Evaluation board(Cyclone III), quartus 8.1 web edition. Since I'm new to Altera, I would like to start with a simple design with an ethernet MAC , then send and recieve packets through...


FPGA's for Ethernet?

Started by Todd in comp.arch.fpga15 years ago 8 replies

Hi all I'm a design engineer trying to evaluate the large number of possibilities for adding Ethernet to our embedded system. So far I've...

Hi all I'm a design engineer trying to evaluate the large number of possibilities for adding Ethernet to our embedded system. So far I've been very impressed by the Altera Cyclone II with NIOS II and free lightweight TCP/IP stack. Adding Ethernet appears to amount to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). Anyone have experience with using the Cyclone II mer...


Need help in capturing serial data using FPGA and ethernet interface

Started by Amir Amin in comp.arch.fpga18 years ago

hello, i want to capture 2 mbps serial data stream through my ethernet card. i already have a Virtex FPGA based hardware and I want to add it...

hello, i want to capture 2 mbps serial data stream through my ethernet card. i already have a Virtex FPGA based hardware and I want to add it this data logging funtionality. I want to use FPGA to convert the received serial data into ethernet format and dump it onto the ethernet interface. Then i can use some port sniffer to capture that data. i just have the vague idea. kidly someone t...


Gigabit Ethernet UDP/IP

Started by Klaus Falser in comp.arch.fpga15 years ago 5 replies

Hello, for a printing application I would like to receive data from a Unix workstation over Gigabit Ethernet (copper) at maximum speed. A...

Hello, for a printing application I would like to receive data from a Unix workstation over Gigabit Ethernet (copper) at maximum speed. A first test showed us that today 2 workstations are able to interchange data over GB Ethernet with about 110 MB/s, nearly at the theoretical limits. The receiver should be implemented with an FPGA, put the data into DDR memory and process the data wi...


FPGA board with multiple Ethernet connections (Gigabit Ethernet)

Started by Anonymous in comp.arch.fpga14 years ago

Hi, I am searching for an FPGA board having multiple gigabit ethernet connectivity support on it. To be more precise, I need to have multiple...

Hi, I am searching for an FPGA board having multiple gigabit ethernet connectivity support on it. To be more precise, I need to have multiple RJ45 connectors and associated logic (PHY) on the FPGA board so that I can process multiple (maximum 24) ethernet streams on the FPGA. Can anyone suggest any such board? or any add-on module which can be hooked up on some particuar FPGA board providing...


How can Spartan-6 interface with 10/100 Mb/s Ethernet?

Started by fl in comp.arch.fpga7 years ago 2 replies

Hi, I read LogiCORE IP AXI Ethernet Lite MAC (v1.01.b), which says that the Ethernet interface is with 10Mb/s 100Mb/s. On its spec, I find that...

Hi, I read LogiCORE IP AXI Ethernet Lite MAC (v1.01.b), which says that the Ethernet interface is with 10Mb/s 100Mb/s. On its spec, I find that the maximum clock for Spartan xc6slx45t AXI4-lite 120 MHz (Target Fmax). I am puzzled about the two categories numbers. 120 MHz is only marginal higher than 100 Mb/s. How can it recover a 100 Mb/s data? Could you explain it to me? Thanks,


Ethernet y MicroBlaze with Spartan 3e starter kit

Started by janigav in comp.arch.fpga12 years ago 1 reply

Hi. I'm trying to communicate a Spartan 3e starter kit revision D whit a PC via ethernet using Microblaze and EDK 10.1, but i don't know how to...

Hi. I'm trying to communicate a Spartan 3e starter kit revision D whit a PC via ethernet using Microblaze and EDK 10.1, but i don't know how to use the ethernet IP EMAClite. If anyone have an example or documentation about it, would be very helpful. Thank you. Javier.


FPGA-Board for Ethernet

Started by bankoo in comp.arch.fpga9 years ago 6 replies

Hi, I am searching a FPGA board for a project where i have to connect an twiste= d pair cable to a FPGA and send&receive packages on a pc. So it...

Hi, I am searching a FPGA board for a project where i have to connect an twiste= d pair cable to a FPGA and send&receive packages on a pc. So it will look l= ike this switch FPGA Board PC UDP will be enough because I dont need any further information from the pac= kages. It will be a 100Mbit/s Ethernet but no standard ethernet like 100base-T. (d= ifferent coding PAM-3)=20 Do you t


TESTAPP_PERIPHERAL FAILED IN ETHERNET

Started by Pablo in comp.arch.fpga15 years ago

Hi, I am tryint to include an ethernet app in my design, but always failed. So I try to probe the code example generated by BSB when you add an...

Hi, I am tryint to include an ethernet app in my design, but always failed. So I try to probe the code example generated by BSB when you add an Ethernet_MAC. Then I plug a crossover cable between PC and Board but the TestApp_Example fails in Ethernet: Test Failed!!!. What kind of Ethernet_MAC configuration must I try?? Is the connection between PC and Board ok or I have to connect the boar...


Nios - Ethernet Frame Format

Started by Colin in comp.arch.fpga17 years ago 3 replies

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is...

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is a CRC trailer does the Nios software and hardware check this automatically? And if there isn't a 32-bit CRC trailer, how can we calculate and add this? Thanx


Nios - Ethernet Frame Format

Started by Colin in comp.arch.fpga17 years ago

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is...

Hi, I would like to know if the Ethernet packets sent through the Nios Ethernet Kit, do they have a 32-bit CRC as the trailer. If there is a CRC trailer does the Nios software and hardware check this automatically? And if there isn't a 32-bit CRC trailer, how can we calculate and add this? Thanx


FPGA prototype board with ethernet interfaces

Started by Vikram in comp.arch.fpga17 years ago 4 replies

Hello All I am new to FPGA world and thinking to start self-project for learning purpose. I am thinking of building ethernet switch as...

Hello All I am new to FPGA world and thinking to start self-project for learning purpose. I am thinking of building ethernet switch as exercise and wondering what are the options I have for development board which has ethernet interfaces (2-4) connected to it. Looking for any other suggestion you have. Thanks -- Vikram


crc on only data or including the address

Started by ashwin in comp.arch.fpga16 years ago 8 replies

Hello everyone, I am trying to transfer data between on board ethernet PHY and the PC. For that i am implementing ethernet packet generator in...

Hello everyone, I am trying to transfer data between on board ethernet PHY and the PC. For that i am implementing ethernet packet generator in the fpga. The MII interface on the fpga has transmit data bus of width 4 bits. So i am sending 64 bytes of frame from the fpga with the most significand bit transmitted first. As you all know ethernet frame consists of preamble,startframe,destin...


EDK on Virtex4 FX using embedded ethernet MAC

Started by Pete in comp.arch.fpga16 years ago 4 replies

Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK offers several...

Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK offers several options for Ethernet MAC type but they are all soft MACs. The embedded MAC is a major selling point for me because of the logic saved and because compiling the soft MACs takes a long time. I will be connecting to a 10/100 switch using the MII port. Is...


Spartan3 JTAG flash In System Programming over Ethernet

Started by Anonymous in comp.arch.fpga13 years ago 4 replies

I am interested in using the Xilinx 10/100 Ethernet solution supported in their Spartan3 eveluation kit. I have a JTAG based flash PROM XCF02S...

I am interested in using the Xilinx 10/100 Ethernet solution supported in their Spartan3 eveluation kit. I have a JTAG based flash PROM XCF02S connected to the Spartan3. I would like to know best way to do the In System Programming of this JTAG based PROM over the ethernet. The Xilinx reference design for the 10/100 ethernet uses Microblaze. We were thinking about putting down GPIO pins fro...