Network Communication Using Nios Daughter Board

Started by Colin in comp.arch.fpga17 years ago

Hi, My partner and I are trying to implement a network bridge using the APEX20KE Nios Development board and Nios Ethernet Daughter Board. ...

Hi, My partner and I are trying to implement a network bridge using the APEX20KE Nios Development board and Nios Ethernet Daughter Board. As part of this network bridge we need to be able to recieve all Ethernet packets and be able to strip the headers (which we have been able to do). And then create new headers, create another Ethernet packet with the new header and send that (which we ...


Ethernet reference design for ML310?

Started by Joseph in comp.arch.fpga16 years ago 3 replies

Is there a simple tutorial or reference design available that implements the ethernet IP from Xilinx? I have stepped through the "Creating a...

Is there a simple tutorial or reference design available that implements the ethernet IP from Xilinx? I have stepped through the "Creating a Linux BSP and System Image for the Base Design" tutorial provided by Xilinx and would now like to incorporate ethernet support as a step closer to building something closer to the MontaVista Linux reference system provided with the board. Any advice or...


Is it possible to implement Ethernet on bare metal FPGA, Without Use of any Hard or Soft core processor?

Started by Swapnil Patil in comp.arch.fpga3 years ago 46 replies

Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? I don't want to...

Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? I don't want to connect any Hard or Soft core processor. also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. So how can it be done? It is not necessary to use spartan 6 b...


Ethernet MAC on Virtex 4

Started by hassoo in comp.arch.fpga10 years ago 8 replies

Hi all, I am new to the world of FPGA. I want to communicate my Virtex 4 XC4VSX35 FPGA to PC using Tri-mode Ethernet MAC IP core. Please give...

Hi all, I am new to the world of FPGA. I want to communicate my Virtex 4 XC4VSX35 FPGA to PC using Tri-mode Ethernet MAC IP core. Please give me any suggestion how to start... Also recommend some basic documentation which helps me understand. Or if there is any better alternative, plz do share it with me... Regards, Hassoo --------------------------------------- Posted ...


tutorial on XPS ethernet MAC lite

Started by bhatti in comp.arch.fpga11 years ago

Hi Kindly if there is any tutorial/example available on xilinx XPS ethernet MAC lite (for Virtex4 PPC), let me know it. Thanks ...

Hi Kindly if there is any tutorial/example available on xilinx XPS ethernet MAC lite (for Virtex4 PPC), let me know it. Thanks --------------------------------------- Posted through http://www.FPGARelated.com


Using xilinx XAUI core in Ethernet design. What is the exact frame format pass through XAUI?

Started by myne...@yahoo.com.cn in comp.arch.fpga14 years ago

We use xilinx xaui core in our Ethernet design, we choose XGMII as our internal interface. And now, I am confused. I found that the data between...

We use xilinx xaui core in our Ethernet design, we choose XGMII as our internal interface. And now, I am confused. I found that the data between START(0xfb) andTERMINATE(0xfd) will all be transmit through XAUI. So, if we use xaui core in Ethernet design, do we need to transmit preamble, sfd and FCS? Now, I think may be we need preamble and sfd to meet XGMII standard, but what about FCS. In 80...


Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"

Started by Colin in comp.arch.fpga17 years ago 2 replies

Hi, I'm trying to use the Nios Ethernet Development Kit to run a simple example program, it build fine, but when I run it it comes up with...

Hi, I'm trying to use the Nios Ethernet Development Kit to run a simple example program, it build fine, but when I run it it comes up with a "spurious interrupt number: 0000 001C" error. Does anyone know how to solve this problem. I'm using the Excalibur Apex development board, Nios 3.0, and the Nios Ethernet Development Kit 2.0. Thanx.


Raggedstone1 Ethernet Modules Available

Started by John Adair in comp.arch.fpga15 years ago

Finally we have the ethernet modules in stock that lots of you are asking for. Apologies to those of you that have been waiting but we have had...

Finally we have the ethernet modules in stock that lots of you are asking for. Apologies to those of you that have been waiting but we have had a few problems getting an assembly slot. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk


Gigabit Ethernet PHY without NDA?

Started by Matt Ettus in comp.arch.fpga13 years ago 5 replies

I've been using a National Semi DP83865 Gigabit Ethernet PHY chip for a while now. It has 4 problems: - Burns 1.25 Watts (and gets hot) -...

I've been using a National Semi DP83865 Gigabit Ethernet PHY chip for a while now. It has 4 problems: - Burns 1.25 Watts (and gets hot) - Needs 2 voltages, 1.8 and 2.5 Volts, and 1.8 is used nowhere else in my system - Can't maintain a connection on 100 meters of Cat-5 - It is a very large chip So I decided to look around for a replacement. I have found candidates from Marvell, Vit...


Re: Checksums

Started by Andreas Ehliar in comp.arch.fpga13 years ago 5 replies

On 2008-06-03, Ambreen Ashfaq Afridi wrote: > hi all, > Im working on a project in FPGAs called "network Traffic Manager" in > verilog...

On 2008-06-03, Ambreen Ashfaq Afridi wrote: > hi all, > Im working on a project in FPGAs called "network Traffic Manager" in > verilog implemented in virtex 4. Im using trimode ethernet MAC core in > it. Now i have to send a packet via ethernet to the other machine and > recalculate the checksum. For that i have to first calculate the > cheksum. Now the problem is tha


Networking Board Recommendation

Started by step...@gmail.com in comp.arch.fpga12 years ago 3 replies

All, Could someone point me to a board or boards that combine a modern FPGA with multiple ethernet PHYs? The only multiple-ethernet board...

All, Could someone point me to a board or boards that combine a modern FPGA with multiple ethernet PHYs? The only multiple-ethernet board that I have discovered is based on a V2P. Thank you in advance. Stephen


Sending and receiving Ethernet traffic

Started by Jean Nicolle in comp.arch.fpga18 years ago 6 replies

I managed to transmit and receive traffic on a 10BASE-T network using some simple Verilog code and 4 pins of an FPGA connected almost directly to...

I managed to transmit and receive traffic on a 10BASE-T network using some simple Verilog code and 4 pins of an FPGA connected almost directly to the wires. Most microcontrollers require an external Ethernet MAC, but it seems that we can do without if we limit ourselves to IP/UDP. I think that there are potentially plenty of interesting applications. The project is working well already, ...


Xilinx Virtex II MAC & PHY. ( HELP)

Started by Tony K in comp.arch.fpga17 years ago 2 replies

Hi I am working with Xilinx Virtex II FPGA. There is a soft core MAC and daughter card PHY. I am not using any kind of Stack. I am trying...

Hi I am working with Xilinx Virtex II FPGA. There is a soft core MAC and daughter card PHY. I am not using any kind of Stack. I am trying to implement Ethernet to Ethernet. I am able to send packet on the wire from the MAC through they PHY and I am able receive these packets back also through the PHY and MAC. I am able to do this loopback through writing bogus source MAC address and my o...


Ethernet on recent FPGAs

Started by Pat Magnits in comp.arch.fpga14 years ago 24 replies

Hi, Am far from being an expert in fpga usage and programming, I was wondering if there exists any ip cores out there that would allow the...

Hi, Am far from being an expert in fpga usage and programming, I was wondering if there exists any ip cores out there that would allow the use of ethernet interfaces on recent FPGAs. For instance say that I have a rather important bandwidth (500Mb/s) and that I want to send that over the Gigabit interface of a Virtex 5 in UDP frames. Is there any blackbox concept IP Core that would al...


URGENT :problem using Ethernet MAC ip core...

Started by vikram in comp.arch.fpga13 years ago 1 reply

hello i am using a virtex 2 pro board to implement a communication system, and want to interface it with my pc (Matlab) via rthernet. for...

hello i am using a virtex 2 pro board to implement a communication system, and want to interface it with my pc (Matlab) via rthernet. for this purpose, i have acquired a Xilinx Ethernet MAC ip core (OPB). i am new to this kind of work, and donot know how to use the core. please tell me, in as simple a way as possible, : 1) what do i get as part of the core? (the hardware descri[tion fi;e...


Sending UDP packets over Ethernet

Started by Fred in comp.arch.fpga13 years ago 9 replies

I've been tasked to write some code for an FPGA to interface to 10BASE- T Ethernet using differential drivers and receivers. The information...

I've been tasked to write some code for an FPGA to interface to 10BASE- T Ethernet using differential drivers and receivers. The information is one way, transmit only! I will have an IP address within the network range, give myself a MAC number and know the MAC and IP address of the destination PC. Do I require any ARP or any other protocol? Will it just work, with the destination PC r...


Ethernet Switch on Configurable Logic now available

Started by Logixa in comp.arch.fpga7 years ago

Now available from our Opencores.org repository a highly configurable Ethernet Switch for FPGA implementations. Check...

Now available from our Opencores.org repository a highly configurable Ethernet Switch for FPGA implementations. Check http://opencores.org/project,esoc for more details.


Lean Ethernet on Digilent board?

Started by Alfredo in comp.arch.fpga16 years ago 2 replies

Has anyone used the Ethernet add-on module for the Digilent Spartan3 board? http://www.digilentinc.com/info/NET1.cfm I want to back into...

Has anyone used the Ethernet add-on module for the Digilent Spartan3 board? http://www.digilentinc.com/info/NET1.cfm I want to back into design, and instead of doing the same old uart/SERDES design I did years ago, I wanted to do something more challenging. Thanks, *** Alfredo.


spartan-3e starter kit and ethernet

Started by Anonymous in comp.arch.fpga15 years ago 3 replies

Hello, I recently purchased a spartan-3e starter kit from Xilinx. (I have so far been unimpressed with the reference designs supplied with the...

Hello, I recently purchased a spartan-3e starter kit from Xilinx. (I have so far been unimpressed with the reference designs supplied with the kit, but that's another subject...) I am trying to use the ethernet connector on the board to communicate with a PC, and so far I have been unsuccessful. I do not want to use a soft-core like picoblaze, I just want to be able to communicate using ...


Looking for Xilinx fpga board that works in Linux and has Ethernet card

Started by Thuy Pham in comp.arch.fpga14 years ago 1 reply

I am looking for a FPGA board which supports some features: 1- PCI interface 2- 1G ethernet port 3- Linux driver support 4- Less...

I am looking for a FPGA board which supports some features: 1- PCI interface 2- 1G ethernet port 3- Linux driver support 4- Less than 1,000 USD Would any one please show me the suitabe cards or give some suggestions. Thanks Thuy