OT: Gigabit Ethernet MAC Throughput

Started by owner in comp.arch.fpga17 years ago 7 replies

Hi, This is somewhat OT, but I can't find a more suitable newsgroup. I am using a Gigabit Ethernet MAC chip from Marv***, which claims...

Hi, This is somewhat OT, but I can't find a more suitable newsgroup. I am using a Gigabit Ethernet MAC chip from Marv***, which claims full line rate (compliance to IEEE 802.3ab). It has an integrated GMAC, PHY/Serdes, and PCI interface (64-bit, 66MHz). On the PCI bus side, we connect it to a Spartan IIe-300 with a Xilinx PCI Logicore. Everything works in the FPGA, PCI read/write trans...


Ethernet MAC wrapper & ML403

Started by misiu in comp.arch.fpga15 years ago

Hello all, I am quite confused about the Ethernet MAC wrapper IP core. In the documentation is written (if I understand correctly) that I...

Hello all, I am quite confused about the Ethernet MAC wrapper IP core. In the documentation is written (if I understand correctly) that I have to provide clk_gtx_clk, clk_phy_tx_clk0, clk_phy_rx_clk0, all are 125 MHz clocks when I am using only EMAC0 and 1Gbps operation. But inside the vhdl files I found hostclk and refclk and information that hostclk must always be connected and refc...


Ethernet PHY and Endianness

Started by Gints in comp.arch.fpga12 years ago

Good Afternoon, I am writing a simple UDP core to send data from a Xilinx S3E to PC via Ethernet sending UDP packets, and have a query...

Good Afternoon, I am writing a simple UDP core to send data from a Xilinx S3E to PC via Ethernet sending UDP packets, and have a query relating to endianness and the PHY: LAN83c185: http://www.smsc.com/media/Downloads_Public/Data_Sheets/83c185.pdf My understanding is that the byte order is Big Endian, thus the most significant byte first: Thus an IP would be sent: C0 then A8 then 00 then...


Regarding connecting two Ethernet Mac Phy

Started by Adnan in comp.arch.fpga14 years ago 1 reply

Hi everyone, I have an FPGA board with two ethernet MAC interfaces. I want to connect both interfaces in a way that transmitter of one EMAC IF...

Hi everyone, I have an FPGA board with two ethernet MAC interfaces. I want to connect both interfaces in a way that transmitter of one EMAC IF is connected with reciever of other and vice versa. I have to have seemless connection. Please let me know whether I would be able to achieve it without putting EMAC core in FPGA. Is there any issues of MII that I am supposed to deal with except clock ...


Bodged up 10/100 Ethernet & USB on FPGA.

Started by Symon in comp.arch.fpga17 years ago

All, I'm building a prototype board and I've the opportunity to try out a few things. One idea I've toyed with is being able to communicate with...

All, I'm building a prototype board and I've the opportunity to try out a few things. One idea I've toyed with is being able to communicate with an FPGA using Ethernet. I've looked at Jean P. Nicolle's site, www.fpga4fun.com , and he's done some interesting stuff. Anyway, I've not got much time for research, my plan is to layout an RJ45 with integrated magnetics, bias the Virtex2P FPGA side ...


Ethernet interfacing

Started by Akshay Eldho Jose in comp.arch.fpga7 years ago 2 replies

Any one did ethernet interfacing in Xilinx Vertex 5.

Any one did ethernet interfacing in Xilinx Vertex 5.


fpga board with onboard 2 ethernet PHY chips?

Started by Neo in comp.arch.fpga17 years ago

Hi, I'm looking for a FPGA board which supports two ethernet PHY chips. Any suggestions? A Virtex-family device would be preferable.

Hi, I'm looking for a FPGA board which supports two ethernet PHY chips. Any suggestions? A Virtex-family device would be preferable.


Help configuring XUP PPC for Ethernet

Started by Islam Ossama in comp.arch.fpga14 years ago 1 reply

Hi everyone, We are a group of Computer Science students working on a project on the XUP board's PowerPC processor core to run an image...

Hi everyone, We are a group of Computer Science students working on a project on the XUP board's PowerPC processor core to run an image processing algorithm and communicate back and forth with a PC across an Ethernet connection. We are having a bit of trouble configuring the board to be able to run our code or any example code properly. We would really appreciate any help since we are nowh...


xiilnx spartan 3 starter kit connection to Ethernet LAN

Started by drma...@gmail.com in comp.arch.fpga16 years ago 1 reply

Hi, I have a Spartan 3 starter board and NET1 ethernet daughter card. I was expecting to use NET1 to connect the starter board to ethernet...

Hi, I have a Spartan 3 starter board and NET1 ethernet daughter card. I was expecting to use NET1 to connect the starter board to ethernet LAN. According to Xilinx tech support the NET1 card can be used only for transferring data between a PC and the starter board, but not for connection as a host on a LAN. Does anybody have a suggestion on how to make the Spartan 3 starter board a host...


FPGA system RAM

Started by Doug Jones in comp.arch.fpga16 years ago 5 replies

I am in the early design stages of an FPGA-based audio / video stream source and sink. The FPGA board will be an ethernet node that will accept...

I am in the early design stages of an FPGA-based audio / video stream source and sink. The FPGA board will be an ethernet node that will accept digitized video from a local video camera for compression as well as digitized audio. The compressed video/audio stream will be streamed out over ethernet. Simultaneously, the FPGA board will accept via incoming ethernet a compressed video/audio st...


Cheap 100mbit/s ethernet MAC/PHY daughterboard ?

Started by msd in comp.arch.fpga17 years ago 1 reply

Hi wo knows a cheap 100mbit/s ethernet MAC/PHY daughterboard (e.g. equipped with LAN91C111 from smsc) to use with an fpga...

Hi wo knows a cheap 100mbit/s ethernet MAC/PHY daughterboard (e.g. equipped with LAN91C111 from smsc) to use with an fpga dev.board? thanks marco


Data width change in opencores Ethernet MAC

Started by pei...@uwiep.com in comp.arch.fpga16 years ago 1 reply

Hello, Just wondering if anyone can let me know if I'm going about this the right way - I'm trying to implement the opencores Ethernet MAC...

Hello, Just wondering if anyone can let me know if I'm going about this the right way - I'm trying to implement the opencores Ethernet MAC on a Xilinx FPGA, but the board I have has too few I/Os. So, I want to reduce the width of the 32bit data inputs and outputs in the wishbone interface to accommodate (I'm about 70 IOBs short). It seems like this should be feasible since the data is d...


implementing ethernet FCS code in verilog

Started by Dilan in comp.arch.fpga14 years ago 4 replies

hi, i am going to use easics tool for generating crc32 verilog code (8bit input) (www.easics.com/webtools/crctool) . i was able to implement...

hi, i am going to use easics tool for generating crc32 verilog code (8bit input) (www.easics.com/webtools/crctool) . i was able to implement correctly.but i need more info to how use this crc to generate FCS of a ethernet packt. i heard about there must be some bit reversal before applying to crc generator. but i am not clear about it .can any one guide me to what have to data stream b...


FPGA+Ethernet

Started by Steve in comp.arch.fpga15 years ago 8 replies

Hi all, I want to add an Ethernet interface to my FPGA board for data transmission. But I'm not sure which scheme I should use. A) There's...

Hi all, I want to add an Ethernet interface to my FPGA board for data transmission. But I'm not sure which scheme I should use. A) There's a PHY on the FPGA board, but I don't have much knowledge or experience on MAC. The protocol seems complicated and not easy to implement in a short time. Is it possible to develop a small and simple MAC? My idea is packing data to form a standard T...


Using Ethernet to control/initialize FPGA

Started by James Ma in comp.arch.fpga16 years ago

Add an Ethernet MAC to your FPGA to enable control from a PC. Simple & easy. No driver programming. Direct control of FPGA state...

Add an Ethernet MAC to your FPGA to enable control from a PC. Simple & easy. No driver programming. Direct control of FPGA state machines, registers & memories. No TCP/IP/UDP needed. Support multiple audio & video streams. Low gate count & low cost, no royalties. www.chipenet.com


ethernet phy- DP83847

Started by ashwin in comp.arch.fpga16 years ago 1 reply

Hello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. The data sheet is on this...

Hello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. The data sheet is on this link http://www.national.com/ds/DP/DP83847.pdf I need to write an ethernet mac in the fpga to send the packets to the PC through the PHY. Initially, to start with i am implementing the transmit module. 1) when i hardware reset the PHY, the link estab...


Ethernet wrapper IP core with ML403

Started by misiu in comp.arch.fpga15 years ago

Hello, I would like to try the Ethernet Wrapper IP core together with the ml403 board and I have a problem making it operational. I have...

Hello, I would like to try the Ethernet Wrapper IP core together with the ml403 board and I have a problem making it operational. I have generated core form generator after that update the constraint file so that all (I think) RXs, TXs and PHY reset nets are connected to the pads. After programing the FPGA I can see that PHY has been reseted and connection has been established but whe...


fpga4fun

Started by Paul in comp.arch.fpga18 years ago 2 replies

Hi I saw this cool project on fpga4fun on 10baseT ethernet. it's so cool needs only 2 lines. like rs-232. I like to try it, but my board has...

Hi I saw this cool project on fpga4fun on 10baseT ethernet. it's so cool needs only 2 lines. like rs-232. I like to try it, but my board has this LXT972 chip (ethernet PHY thingy, like those MAXxxxx rs-232 voltage convertor thingy) sitting between my x2cv2000 fpga and the connector. it has so many pins that i don't know what to do with them. Can someone know about voltage and stuff tel...


ethernet EMAC cores available for Microblaze

Started by kurapati in comp.arch.fpga16 years ago

H Xilinx offers different IP cores for ethernet. like opb_ethernet plb_ethernet, plb_temac, plb_gemac, ll_temac, ll_gemac, etc. Which of...

H Xilinx offers different IP cores for ethernet. like opb_ethernet plb_ethernet, plb_temac, plb_gemac, ll_temac, ll_gemac, etc. Which of those IPs can be used to have a gigabit MAC using Microblaz processor. Recently EDK servicepack 3 has been released and there is a plb_tema but I could not find the posibilty to use it with microblaz processor. And there is a 1-Gigabit MAC available a...


Spartan 3E starter kit expansion boards - Gb ethernet & video

Started by ereader in comp.arch.fpga14 years ago

I have been thinking about doing 1 or 2 expansion boards for the Spartan 3E starter board to add Gb ethernet & camera capability. Has anyone...

I have been thinking about doing 1 or 2 expansion boards for the Spartan 3E starter board to add Gb ethernet & camera capability. Has anyone done this already & is willing to sell a copy ? Save me some work.