WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs

Started by Frank in comp.arch.fpga15 years ago 2 replies

I've been looking all over for a board with a Xilinx V4 LX160 or 200 FPGA and 2 10/100 Ethernet PHYs. Closest I got was a board from Avnet...

I've been looking all over for a board with a Xilinx V4 LX160 or 200 FPGA and 2 10/100 Ethernet PHYs. Closest I got was a board from Avnet that only had 1 PHY. Know where to find one? Please let me know. Many thanks.


Implementing a communication protocol for data transfer over TCP on an FPGA

Started by Andre Renee in comp.arch.fpga15 years ago 7 replies

Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the...

Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the HTG-V4PCIe evaluation board, which is a Xilinx Virtex-4 PCI Express Development Board from HighTech Global (http://www.hitechglobal.com/boards/v4pcie.htm). It features the Marvell Alaska 88E1111 Gigabit-Ethernet PHY which I use in combination with t...


XC2VP70 FPGA board suggestions

Started by Anup Kumar Raghavan in comp.arch.fpga18 years ago 1 reply

Can I get suggestions for FPGA development boards that house the XC2VP70/125 Virtex 2 Pro FPGA? I have read the DINI specs and they seem to be...

Can I get suggestions for FPGA development boards that house the XC2VP70/125 Virtex 2 Pro FPGA? I have read the DINI specs and they seem to be the only one I can find that supports this FPGA. I want a board I can use to test network protocols like gigabit ethernet, and hence want to hook up either fibre or coax-ethernet cable to the board. Thanks Anup


Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF

Started by Anonymous in comp.arch.fpga15 years ago 5 replies

Hello, I am trying to get the Virtex-4 Ethernet MAC Wrapper IP Core up and running on my Avnet Virtex-4 FX12 Mini Module...

Hello, I am trying to get the Virtex-4 Ethernet MAC Wrapper IP Core up and running on my Avnet Virtex-4 FX12 Mini Module (http://tinyurl.com/ yqc6ah), and I am having all sorts of problems. One of the main problems right now seems to be my understanding of the UCF file and what to edit or not to edit, since the rest of the design should be already set up fine from what I have read in the u...


Matlab, RS-232, Ethernet

Started by satyam in comp.arch.fpga14 years ago 8 replies

Hi, I want to interface matlab with the Xilinx Virtex-II pro board. Intent is to give input from matlab to the FPGA and to read the ouput of...

Hi, I want to interface matlab with the Xilinx Virtex-II pro board. Intent is to give input from matlab to the FPGA and to read the ouput of FPGA in matlab. Problem is in interfacing speed. I need high speed interface, of the order of 2 mega bits per second (Mbps). Seems RS-232 will be inadequate for my purpose. From Documents interface through ethernet seems to be a viable option but I...


GEMAC and MGT on ML300

Started by Jeffsen in comp.arch.fpga17 years ago 2 replies

Dear all, I have a Xilinx-ML300 at hand,and want to test the Gemac core by connect FPGA with PC via Gigabit-Ethernet. The problem is on ML300 the...

Dear all, I have a Xilinx-ML300 at hand,and want to test the Gemac core by connect FPGA with PC via Gigabit-Ethernet. The problem is on ML300 the RJ45 connector is not for gigabit ethernet. There is optical fiber link avaiable and also MultiGigabitTransceivers(MGTs) avaiable. One solution is using the optical links. While another people told me to use MGT to implement the gigabitEthernet? Is that ...


UDP problems with Xilinx EDK 7.1

Started by jswestra77 in comp.arch.fpga16 years ago 1 reply

Hi All, I am having some problems using UDP LwIP calls in EDK7.1. Let me give some details. I am trying to create an Ethernet bridge using the...

Hi All, I am having some problems using UDP LwIP calls in EDK7.1. Let me give some details. I am trying to create an Ethernet bridge using the Memec V4LX60MB board. The board has a 10/100 Ethernet PHY connected to a Virtex-4 LX60 FPGA. I have the EDK project from Xilinx appnote XAPP663 as a starting point. After changing the pinouts and SRAM to match the Memec board, I can get this project...


OPB Emac : Sending a frame

Started by Surya in comp.arch.fpga14 years ago

Hello, I am trying to send one single ethernet frame using Ethernet lite core in the XUP2VP board from Digilent Inc. I am unable to do so. I...

Hello, I am trying to send one single ethernet frame using Ethernet lite core in the XUP2VP board from Digilent Inc. I am unable to do so. I am trying to capture the sent packet using Wireshark (Ethereal). However, i am not receiving any packet. But if i repeat the send functional call in a for loop from 46 bytes to 1500 bytes, the frames are received in the packet capture utility. (though...


Communication between FPGA and PC with ethernet

Started by Roggey in comp.arch.fpga16 years ago 12 replies

Hello I have to make an connection to a FPGA-borad. http://www.celoxica.com/products/rc300/default.asp This board only supports ethernet...

Hello I have to make an connection to a FPGA-borad. http://www.celoxica.com/products/rc300/default.asp This board only supports ethernet communication with the mac-layer. Now I have to build an app that can send data(in my case images) to the board. My question is now how can i send data using the mac-layer only from a c++ programm. I do not think that we are using(or is possible...


NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent

Started by logjam in comp.arch.fpga15 years ago 3 replies

I just bought the S3EBOARD from Digilent (http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable) to be my...

I just bought the S3EBOARD from Digilent (http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable) to be my first FPGA board. For my first project I want to make an ADM3 serial terminal emulator with telnet over ethernet ability. It will just be a character based display with PS/2 keyboard for input and VGA for output, and the serial port for the termi...


Send IP packets at the Ethernet level with VIRTEX4

Started by pho in comp.arch.fpga16 years ago 2 replies

Hello, I would to use a simple/easy way to send, in multicast address, some IP packets fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I...

Hello, I would to use a simple/easy way to send, in multicast address, some IP packets fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I don't want to use the PowerPC and its EMAC controller. I read that the PHY interface can be set in hardware register but I don't know if I can use the PHY interface as a simple FIFO. Is there someone who uses that way to send IP packets to a networ...


10 Gigabit Ethernet FPGA boards...

Started by Nicholas Weaver in comp.arch.fpga16 years ago 1 reply

We are looking at some research prototyping of IDS work. We are currently doing 1 Gbps prototyping on a current board, but are looking at 10...

We are looking at some research prototyping of IDS work. We are currently doing 1 Gbps prototyping on a current board, but are looking at 10 Gbps prototyping. Are there any FPGA boards available with: SRAM (a few MB minimum) A large FPGA 2 or more! 10 Gigabit ethernet interfaces. As a bonus, 2 10-GigE plus a PCI slot would be ideal. We MIGHT be able to get away with a single 10 Gig...


Does anyone have a NIOS Ethernet Development Kit?

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

My company is attempting to produce a secure switch based on the Altera Stratix II (EP2S60) board. Unfortunatley, Altera no longer sells...

My company is attempting to produce a secure switch based on the Altera Stratix II (EP2S60) board. Unfortunatley, Altera no longer sells the Ethernet Development Kit. We're attempting to build a replica of the daughter card that came with the kit from Altera's designs, but it would be useful to have a working example of the card for comparison purposes. So if anyone has a daughter card bas...


ANNC: Secure FPGA Configuration Over Ethernet Webcast

Started by bart in comp.arch.fpga14 years ago

Lattice is holding a webcast tomorrow, Thursday, May 31, "Secure FPGA Configuration Over Ethernet," covering a Verilog / FPGA based...

Lattice is holding a webcast tomorrow, Thursday, May 31, "Secure FPGA Configuration Over Ethernet," covering a Verilog / FPGA based design application of a reconfigurable soft embedded microprocessor system. The presenter will be Johnathan Mantey, from our applications engineering group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be a...


Avnet Virtex-4 FX12 mini module

Started by Anonymous in comp.arch.fpga15 years ago 5 replies

Hello, I have recently bought Avnet Virtex-4 FX12 mini module. I am trying to implement the Gigabit ethernet communication between the...

Hello, I have recently bought Avnet Virtex-4 FX12 mini module. I am trying to implement the Gigabit ethernet communication between the FPGA and the host PC. Can anyone give me some hints to get started? I have not found the data sheet for the giga bit ethernet physical transceiver from Broadcom that the board has on it. The part number for it is BCM5461. If any one has the data shee...


How to Use Spartan 6 Ethernet Port

Started by Zinabu Haile in comp.arch.fpga8 years ago

Hi all I need your help.I met a problem when I use the SPARTAN-6 FPGA board (xc6slx45-csg324c).I'm currently working on a project that I...

Hi all I need your help.I met a problem when I use the SPARTAN-6 FPGA board (xc6slx45-csg324c).I'm currently working on a project that I need to send data from my PC to FPGA board using Ethernet port. 1. How can I assign IP to the FPGA board,if possible. or 2. How can I communicate with the FPGA board from my PC with some LED indicator Thanks


System Packet Interface?

Started by freechip in comp.arch.fpga16 years ago 1 reply

Hi, I am doing a project on a 10GB Ethernet. I am going to use a FPGA with a 10Gb Ethernet Mac Core. If I use a NIOS II, it's not necessary...

Hi, I am doing a project on a 10GB Ethernet. I am going to use a FPGA with a 10Gb Ethernet Mac Core. If I use a NIOS II, it's not necessary for me to purchase a development board supporting the SPI (System Packet Interface)? This interface is used between a FPGA and NPU. Thank you


Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer

Started by James Ma in comp.arch.fpga15 years ago 1 reply

Add 4 Gb/s Ethernet links to FPGA systems easily & at low cost. High bandwidth, low latency control & data transfers. Low gate count & low...

Add 4 Gb/s Ethernet links to FPGA systems easily & at low cost. High bandwidth, low latency control & data transfers. Low gate count & low pin count. Define your own protocol. No TCP/IP/UDP processing required. Connection through standard switches or direct to PCs. Simple & easy. No driver programming. www.chipethernet.com


Coregen GMII embedded ethernet MAC

Started by in comp.arch.fpga15 years ago 1 reply

I have been trying to implement Virtex-4 Tri-Mode Embedded Ethernet MAC Wrapper v4.3(GMII) from coregen in ISE. All guides tell me to use a...

I have been trying to implement Virtex-4 Tri-Mode Embedded Ethernet MAC Wrapper v4.3(GMII) from coregen in ISE. All guides tell me to use a VHO- file, which should contain an instantiation template, but coregen doesn't create such template file for this core. And the template in ISE is blank. I should also get an edn or ngc netlist file which isn't there either. The user guide specifies ...


Testbench failures for Opencores Ethernet mac

Started by Anonymous in comp.arch.fpga16 years ago

Hello, I'm fairly new to this - just got started running the testbench for the Opencores Ethernet core. I'm using Modelsim SE64 Plus 6.0b in a...

Hello, I'm fairly new to this - just got started running the testbench for the Opencores Ethernet core. I'm using Modelsim SE64 Plus 6.0b in a Solaris 5.10 environment. I get a few test failures when running the testbench: Heading: MIIM MODULE TEST At time: 8991769 Test: TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE ) ...