FPGA : Open core FFT

Started by bijoy in comp.arch.fpga11 years ago 4 replies

Hi all, Does any one used Open core FFT. I am trying to use it, but what my simulation results shows is that the performance of the FFT does...

Hi all, Does any one used Open core FFT. I am trying to use it, but what my simulation results shows is that the performance of the FFT does not match with the other FFT cores available from other vendors(eg. xilinx). The magnitude of the result seems matching except the attenuation of the side lobs is not so good. But what i am afraid is that the phase response of the FFT result is ve...


use of radix-2 ffts

Started by Bob in comp.arch.fpga14 years ago 1 reply

Hello again, Can a radix-4 fft be used to construct any type of radix-2 fft. e.g. can I manipulate a 64 pt radix-4 fft to give me a 128 pt...

Hello again, Can a radix-4 fft be used to construct any type of radix-2 fft. e.g. can I manipulate a 64 pt radix-4 fft to give me a 128 pt radix-2 fft ? If so, is the radix-2 fft of any use in dsp as it usually results in larger and slower ffts than the radix-4 version. As always thanks for all replies. Bob Carter -- My ignorance is shameful, but I would rather be ashamed than igno...


FFT and etc on a cycloneII or III help/sugestions.

Started by LC in comp.arch.fpga10 years ago

Hello, I need some advise... I'm trying to find my way for having an FFT running on a FPGA (along with some other easy stuff) Before...

Hello, I need some advise... I'm trying to find my way for having an FFT running on a FPGA (along with some other easy stuff) Before switching to the option of writing the FFT VHDL myself,I was exploring what existing codes I could use. The Altera FFT-Megacore is a possibility although may have trouble to pay for it since this is for an hobby application not for a commercial product....


checking the FFT cores on Xilinx FPGAs

Started by Vivek Menon in comp.arch.fpga11 years ago

Hi, I am using a FFT core block on Xilinx Virtex-4 FPGA. On simulating a 1024 point FFT with a 64 bit 10 MHz PRBS, I seem to see the FFT...

Hi, I am using a FFT core block on Xilinx Virtex-4 FPGA. On simulating a 1024 point FFT with a 64 bit 10 MHz PRBS, I seem to see the FFT data coming out as steps of zeros and FFs. My ADC samples this data at 1.5GHz, so the peak is at the very end of the spectrum as per Matlab simulations I would like to know if there are any more ways to check the FFT core in realtime by probably giving in ...


Regarding FFT & IFFT CORE IN XILINX

Started by varun_agr in comp.arch.fpga6 years ago

Sir I am trying to use FFT 5.0 core in xilinx as follows for 50 hz Sin WAVE(THROUGH ADC)for noise removal 1. 64 Transform size 2. Radix-2 burst...

Sir I am trying to use FFT 5.0 core in xilinx as follows for 50 hz Sin WAVE(THROUGH ADC)for noise removal 1. 64 Transform size 2. Radix-2 burst mode 3.I/p data width 8 bit 4.Scaled 5. Natural order(without cylix prefix) I want to know what is the value of scale_sch. Further I want to use inverse FFT for the O/P fft i.e XK_REAL AND XK_IMA. and display the same sine wave via DAC. So what is...


Confused about FPGA devices recommended by Xilinx for my FFT project

Started by Telenochek in comp.arch.fpga10 years ago 2 replies

Hi everyone. I have selected spartan 3E family for an FFT project due to its low cost. The FFT core (v 4.0) specs say that for spartan3E...

Hi everyone. I have selected spartan 3E family for an FFT project due to its low cost. The FFT core (v 4.0) specs say that for spartan3E devices, the footprint is as follows (see table) and they "recommend" the device in the table. FFT =EF=BB=BFLength Slices Block RAMs 18x18 Mults Device ---------------------------------------------------------------------------= --...


FFT on an FPGA

Started by Raymond in comp.arch.fpga11 years ago 24 replies

Hi there. I am thinking about to use a Xilinx FPGA to take FFT on some data. Xilinx provide a free FFT core that I most likely can use. I...

Hi there. I am thinking about to use a Xilinx FPGA to take FFT on some data. Xilinx provide a free FFT core that I most likely can use. I need a windowing function (Like hamming) for that/a FFT function. I have at the moment no idea of how to handle floatingpoints numbers in an FPGA, further I have no ideas for any workarounds. Does anyone have some Ideas/Solutions to that? Raymon...


Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

Started by makhan in comp.arch.fpga9 years ago 2 replies

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the...

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the module with the generated xco, I am now trying to simulate the module. The hierarchy is as follows: fft_tb => fft_top => fft.v (generated by coregen) I am using a custom script as follows: ############################################# vlib work vlog fft


FFT on Virtex-II (Desperation Imminent)

Started by John Plows in comp.arch.fpga14 years ago 3 replies

Hello A collegue and I are trying to implement a 256 point FFT on a Virtex-II. The problem we are having is finding a way to transfer the...

Hello A collegue and I are trying to implement a 256 point FFT on a Virtex-II. The problem we are having is finding a way to transfer the calculated FFT data off the FPGA so we can display it (preferably in Matlab). If anyone knows of a tool for uploading/downloading to/from the block RAM on the Virtex-II, please let us know. If anyone has any information on how to interface to t...


FPGA/DSP Expert - business partner for innovative FFT

Started by Seung in comp.arch.fpga14 years ago 15 replies

Hello I have a patent and recently added one more on innovative FFT algorithm and architecture. If you're a business minded expert on FPGA...

Hello I have a patent and recently added one more on innovative FFT algorithm and architecture. If you're a business minded expert on FPGA with interests in DSP, this is a great opportunity. Our FFT is 'the' optimal HW solution as follows: 1. Minimum HW complexity: 100% HW utilization 2. Suitable for super fast pipelined FFT: only local data flow - not based on butterfly algorithm 3. ...


How to calculate IFFT based on FFT result?

Started by Yao Sics in comp.arch.fpga10 years ago 2 replies

Dear All, I just wonder if there is a simple way to calculate IFFT based on FFT results? I was trying to configure xilinx FFT coregen v3.1...

Dear All, I just wonder if there is a simple way to calculate IFFT based on FFT results? I was trying to configure xilinx FFT coregen v3.1 to perform IFFT operation, but no matter how hard I tried, the result is the same as FFT. Strange! The timing is exactly based on the FFTv3.1 datasheet. Assert fwd_inv_we ='1', and fwd_inv=' 0', and then de-assert fwd_inv_we. If this problem can n...


IP Coregen: FFT v2.1 IP core regd.

Started by Anand in comp.arch.fpga13 years ago

Hi, In my design, I am using the FFT v2.1 IP core thats available in the IP Core generator that comes along with Xilinx ISE 6.2. I want to use...

Hi, In my design, I am using the FFT v2.1 IP core thats available in the IP Core generator that comes along with Xilinx ISE 6.2. I want to use the scaling option (SCALE_SCH). I dont know how to derive the scaling schedule. I am configuring the IP core to do 64 point FFT with 8-bit inputs. Any pointers or suggestions is highly appreciated. Thanks. Sincerely, An


Down Sample, FFT

Started by Thomas in comp.arch.fpga14 years ago
FFT

When I simulate my System Generator design, the following error is reported: "Although the behavior of this block, as configured, could be...

When I simulate my System Generator design, the following error is reported: "Although the behavior of this block, as configured, could be simulated, it will not be possible to target it to hardware because: --- Cannot be synthesized and it does not map to cores because the FFT core must be run at the system clock rate" The problem apears when I put a Down Sample block before the FFT i


IP Coregen: FFT v2.1 IP core regd.

Started by anand in comp.arch.fpga13 years ago

Hi, In my design, I am using the FFT v2.1 IP core thats available in the IP Core generator that comes along with Xilinx ISE 6.2. I want to...

Hi, In my design, I am using the FFT v2.1 IP core thats available in the IP Core generator that comes along with Xilinx ISE 6.2. I want to use the scaling option (SCALE_SCH). I dont know how to derive the scaling schedule. I am configuring the IP core to do 64 point FFT with 8-bit inputs. Any pointers or suggestions is highly appreciated. Thanks. Sincerely, Anand


Question on 2048 point FFT( Basic)

Started by aj in comp.arch.fpga12 years ago 1 reply

Hello FFT guru's I am implementing 2048 point FFT on Virtex as a part of my small project at uni. i want to put couple of questions.. please...

Hello FFT guru's I am implementing 2048 point FFT on Virtex as a part of my small project at uni. i want to put couple of questions.. please help me to your best as i am a starter...:) I have gone through couple of IEEE papers and i have found that i should use (Mixed Radix alg).i.e. like Radix4 and Radix2 butterflies to implement this algorithm. i have an understanding to use total of 6...


FFT help

Started by Jaksa in comp.arch.fpga11 years ago 10 replies

Hi. I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 points (can be generic too)). Can Anybody help me, please. Any kind...

Hi. I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 points (can be generic too)). Can Anybody help me, please. Any kind of help would help me. Thanks people


fft size in fpga

Started by PJ in comp.arch.fpga14 years ago 3 replies

Hello, I am implementing a 128 point real Radix-2 fft, data and coefficient widths are 16 bit. I am synthezising it for use in an FPGA....

Hello, I am implementing a 128 point real Radix-2 fft, data and coefficient widths are 16 bit. I am synthezising it for use in an FPGA. However, it is taking a very long time to synthesize. (approx 3 days using Leonardo on a 2 GHz machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram required by the fft will be internal to the FPGA Will this design take up all the space ...


comparing hardware architecture

Started by Marvin L in comp.arch.fpga1 year ago
FFT

Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite sure which one to...

Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite sure which one to use Do you guys have any suggestions for FFT and DCT regarding implementation ? I am now reading on NEDA and Radix. Besides, how would you guys implement DoG (Difference of Gaussian) in hardware ? Thanks !


comparing hardware architecture

Started by Marvin L in comp.arch.fpga1 year ago 1 reply
FFT

Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite sure which one to...

Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite sure which one to use Do you guys have any suggestions for FFT and DCT regarding implementation ? I am now reading on NEDA and Radix. Besides, how would you guys implement DoG (Difference of Gaussian) in hardware ? Thanks !


FFT using logic gates only

Started by moindsp in comp.arch.fpga6 years ago 9 replies

I intend to implement FFT using Logic gates only , by this i mean i have written verilog code of FFT for xilinx spartran III, I can visualize it...

I intend to implement FFT using Logic gates only , by this i mean i have written verilog code of FFT for xilinx spartran III, I can visualize it in Xilinx ISE 13.1 using technology schematic. But its still high level abstraction, can someone guide me how to generate text file / other format file that describes the whole implementation using AND OR , XOR, NAND , NOR gate only Regards mo...