## Some questions about FFT implementation

Started by in comp.arch.fpga13 years ago 9 replies

Hello, I am working with FFT v.3.2 from Xilinx. Some questions relate directly to that core, some do not. 1. Why is block floating point...

Hello, I am working with FFT v.3.2 from Xilinx. Some questions relate directly to that core, some do not. 1. Why is block floating point unavailable for Pipelined/streaming FFT? Is it because the dynamic range is too hard to predict? 2. a) Is the output of A/D converter fixed point (generally)? b) Then only division can introduce floating point, right? 3. For the output ordering, the ou...

## All-real FFT for FPGA

Started by in comp.arch.fpga3 years ago 34 replies

So, there are algorithms out there to perform an FFT on real data, that save (I think) roughly 2x the calculations of FFTs for complex...

So, there are algorithms out there to perform an FFT on real data, that save (I think) roughly 2x the calculations of FFTs for complex data. I did a quick search, but didn't find any that are made specifically for FPGAs. Was my search too quick, or are there no IP sources to do this? It would seem like a slam-dunk for Xilinx and Intel/Altera to include these algorithms in their FFT li...

## FFT core has reversed output data

Started by in comp.arch.fpga11 years ago 6 replies

Hello, I'm implementing a autocorrelation function using a fft and ifft hard core (v6.0) on a Virtex5. When starting the fft, I see at the...

Hello, I'm implementing a autocorrelation function using a fft and ifft hard core (v6.0) on a Virtex5. When starting the fft, I see at the output that the result is reversed in the frequency domain. Example: The input signal is a sinus with a frequency of 2 Hz. As output signal I expect a dirac impuls at the beginning (imaginary). -> f(0)=0; f(1)=0; f(2)=1; f(3)=0; ?; f(N-3)=0; f(N-2)=-1; f

## xilinx FFT core simulation

Started by in comp.arch.fpga9 years ago

Hi all, I am trying to simulate xilinx fft core. I have calculated the bin size. But i do not know how to view that bin number in...

Hi all, I am trying to simulate xilinx fft core. I have calculated the bin size. But i do not know how to view that bin number in Modelsim. For example, If my input signal frequency is 10Hz, Sampling rate is 50, and FFT point is 1024,my Bin size is 204.8. How do i see this with Modelsim. Please guide me. Thanks in advance Parvathi -------------------------...

## 1024 POINTS FFT V2.0 Xilinx Core

Started by in comp.arch.fpga16 years ago

Hi everybody!! I trying to use the core "1024 points fft v2.0" from Xilinx, but I have the problem that I don't get the correct result. I'm...

Hi everybody!! I trying to use the core "1024 points fft v2.0" from Xilinx, but I have the problem that I don't get the correct result. I'm using a constant input of 0001(Hex) for real and 0000(Hex) for imaginary. During the intermediate steps of the fft, the core seems to be coming up with strange values that it writes to memory and the error propagates to the output. I have simulated...

## Xilinx FFT core configured in natural order

Started by in comp.arch.fpga11 years ago 1 reply

Structural simulation of FFT core reveal the frequency to bin (XK_IDX) mapping are bit reversed when the FFT core is configured to output...

Structural simulation of FFT core reveal the frequency to bin (XK_IDX) mapping are bit reversed when the FFT core is configured to output in streaming, natural order. Real time swapping of the frequency needs FIFO of 2^N deep. Can anyone help me to implement a more optimized freq swap method.

## Xilinx LogiCore FFT 3.2

Started by in comp.arch.fpga12 years ago 1 reply

Hi All, I am using the Xilinx Core Genenator to generate the FFT core for my design. But when I tried to simulate with a random noise input...

Hi All, I am using the Xilinx Core Genenator to generate the FFT core for my design. But when I tried to simulate with a random noise input with N = 128, the output xk_re and xk_im are all between -5 and 5 which is obviously not the correct result. Matlab result show the fft output in order of 100. I used fixed length of 128 and tried Radix-4 and Radix-2 implemenation options with 16bi...

## looking for FFT core

Started by in comp.arch.fpga11 years ago

I'm trying to find a 64-point FFT/IFFT core. Target is Actel IGLOO family. Needs to run fast enough to complete in 3.2us, which is tough in an...

I'm trying to find a 64-point FFT/IFFT core. Target is Actel IGLOO family. Needs to run fast enough to complete in 3.2us, which is tough in an IGLOO. Actel has a free FFT core but it is not quite fast enough. It's a radix-2 core, which is not optimal for this application. Radix-4 would be better. I've looked at the cfft core on Opencores and it may work for us, but also want to check co...

## Xilinx FFT

Started by in comp.arch.fpga14 years ago

Hello, I am trying to connect a FFT module generated with coregen to a microprocessor. The problem is that the microprocessor works...

Hello, I am trying to connect a FFT module generated with coregen to a microprocessor. The problem is that the microprocessor works with floating data in IEEE754 format and the xilinx FFT module accepts, fixed point and block-floating point. How can I convert the data from the microprocessor to one the core understand. Regards Javier Castillo

## FFT IP CORE: XK_INDEX???

Started by in comp.arch.fpga13 years ago

When I use the xfft2.0 core to simulate a 1024_point FFT by the ModelSim. Why does the FFT's behavioral simulation fail with block RAM address...

When I use the xfft2.0 core to simulate a 1024_point FFT by the ModelSim. Why does the FFT's behavioral simulation fail with block RAM address errors, # **Warning:Undefined input WEA. Setting output DOUTA to X # Time: 22600 ps Iteration: 2 Instance: /topo/xlxi_1/xlxi_1/u0/arch_b/xfft_inst/dpm0/dpm_inst # ** Warning: Invalid address ADDRA : UUUU1010. Entire memory contents will be set to 'X'....

## FFT with FPGA

Started by in comp.arch.fpga14 years ago 4 replies

Hello, I want to implement a 128bit FFT with FPGA, do you have any reference design for me? Thanks in advance, Mike

Hello, I want to implement a 128bit FFT with FPGA, do you have any reference design for me? Thanks in advance, Mike

## FFT for an arbitrary number of points (not power of 2)

Started by in comp.arch.fpga12 years ago 13 replies

Hi, I'd like to ask experts here about ideas to perform a FFT on an arbitrary number of points (for real data). The cores usually found for...

Hi, I'd like to ask experts here about ideas to perform a FFT on an arbitrary number of points (for real data). The cores usually found for an FPGA implementation only permit FFTs on a number of points that is a power of 2. In our particular case however, we need to be able to do an FFT on a vector of say, 1025 points. Our current algorithm is to zero-pad this vector to 2048 points. ...

Started by in comp.arch.fpga13 years ago

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as my input (which is...

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as my input (which is digital representation of sinusoidal wave shown below) to test the real-time functionality 0 30273 23170 -12539 -32767 -12539 23170 30273 I'm not sure if the above data would show up in the correct format in the newsgroup, but each line repre...

Started by in comp.arch.fpga13 years ago 2 replies

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as my input (which is...

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as my input (which is digital representation of sinusoidal wave shown below) to test the real-time functionality 0 30273 23170 -12539 -32767 -12539 23170 30273 I'm not sure if the above data would show up in the correct format in the newsgroup, but each line repre...

## FFT Ccre

Started by in comp.arch.fpga10 years ago

Hi, Where can I get the information on resource usage (and current consumption) of the FFT cores for Altera devices (specifically 32k to 512k...

Hi, Where can I get the information on resource usage (and current consumption) of the FFT cores for Altera devices (specifically 32k to 512k fixed point for Stratix family). I tried a web search but no decent results. Nagaraj

## How to add a peripheral IP generated by Coregen to EDK?

Started by in comp.arch.fpga13 years ago 1 reply

Hi, I'm trying to add an IP(FFT), generated by Coregen, to an EDK project. I have created a new custom IP in EDK and added the vhdl code of...

Hi, I'm trying to add an IP(FFT), generated by Coregen, to an EDK project. I have created a new custom IP in EDK and added the vhdl code of FFT into user_logic.vhd file, and imported it to the EDK project, but I got three errors: ERROR:NgdBuild:604 - logical block 'fft_ip_0/fft_ip_0/USER_LOGIC_I/fft/U3' with type 'fft128' could not be resolved. A pin name misspelling can cause this, a...

## problem in simulating FFT core on ISE 7.1

Started by in comp.arch.fpga13 years ago 1 reply

hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on modelsim...also i...

hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on modelsim...also i have downloaded "radix 2 fft core" from xilinx core generator examples on xilinx site but failed to simulate it.the error msg in modelsim is as under... ------------------------------------------------------------------------------------------------ ---------

## Parametrized, synthesizable FFT engine

Started by in comp.arch.fpga6 years ago 1 reply

Hi, I have just published a simple, parametrized synthesizable FFT engine, which allows the user to define the length of FFT (as power of...

Hi, I have just published a simple, parametrized synthesizable FFT engine, which allows the user to define the length of FFT (as power of two), define the format of the numbers and adjust the engine to the latency of the "butterfly block". I couldn't find similar open source solution, so I decided to publish mine. Of course it is the user's responsibility to implement the "butterfly block"...

## Xilinx FFT core's IFFT function not working? Dun Xilinx TEST their cores before releasing them?

Started by in comp.arch.fpga11 years ago 3 replies

Hi, has anybody used the FFT v4.1 core from Xilinx Core generator before to do IFFT? This is the scenario: - I am using this config of the...

Hi, has anybody used the FFT v4.1 core from Xilinx Core generator before to do IFFT? This is the scenario: - I am using this config of the FFT core with the selected configurations -pipelined, streaming -unscaled. input wave is 24 bits. output is 34 bits. coefficients also 24 bits input 1) I use matlab to generate 24 bit complex waveform and save it into text file 2) I run my...

## What the switch of FFT implementation in FPGA for

Started by in comp.arch.fpga10 years ago 1 reply

Hi, I look at the FFT core description of Xilinx and I do not understand the function of switch in the diagram. There are two switches in...

Hi, I look at the FFT core description of Xilinx and I do not understand the function of switch in the diagram. There are two switches in the FFT LogiCore diagram, at the both sides of Buttfly. One switch connects the output of RAM block, which the other switch connects to the RAM input. I think the data input and output of RAM can directly connect to the butterfly, because the different RAM...