FFT IP CORE: XFFTV2.0

Started by Little_orange in comp.arch.fpga13 years ago 1 reply
FFT

Who has once used the fft ip core: xfft v2.0? Can you gave me some advice?

Who has once used the fft ip core: xfft v2.0? Can you gave me some advice?


Xilinx Pipelined/Streaming FFT Architecure?

Started by onkars in comp.arch.fpga9 years ago 3 replies

Hi, Can anyone tell me whether the Xilinx Pipelined FFT arch uses R2SDF or R2^2SDF? Regards, Onkar ...

Hi, Can anyone tell me whether the Xilinx Pipelined FFT arch uses R2SDF or R2^2SDF? Regards, Onkar --------------------------------------- Posted through http://www.FPGARelated.com


FPGA : FFT

Started by bijoy in comp.arch.fpga13 years ago 1 reply
FFT

Hi I wanted to implement FFT in FPGA. I would like to do it using the CORDIC technique. Can anyone help to understand the...

Hi I wanted to implement FFT in FPGA. I would like to do it using the CORDIC technique. Can anyone help to understand the technique. Matlab or C equivalent will be help ful rgds bijoy


how to map kernel element of FFT to VIRTEX Pro Board

Started by aj in comp.arch.fpga14 years ago 1 reply

my project leader wants me to fit the elements of Fast Fourier Transfer including Memory to VirtexII pro board.. to start with he has asked me...

my project leader wants me to fit the elements of Fast Fourier Transfer including Memory to VirtexII pro board.. to start with he has asked me to map kernel element of FFT and try to Map it on VIRTEX Pro Board........How will i start from the scratch. I am new in FFT... any help will be highly appreciated thanks in advance Aj


FFT implementation in Xilinx's Spartan 3

Started by biot in comp.arch.fpga14 years ago 3 replies

Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-3 starter kit. I would...

Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-3 starter kit. I would like to know how many months it will take me to fully design it. As a novice i would like to know few suggestions and references for my project. I need help. I don't know from where to start.


[Newbie] 64-point complex FFT with 32 bit floating-point representation

Started by Franco Tiratore in comp.arch.fpga13 years ago 10 replies
FFT

Hi all. I'm currently trying to understand whether or not it is possible to implement a 802.11a-compliant OFDM modulator/demodulator on an...

Hi all. I'm currently trying to understand whether or not it is possible to implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA. As far as I understand, the critical part of the project is the 64-point complex FFT with 32 bit floating-point representation (each real or complex number is represented in 32-bit floating-point). The FFT block should perform this calculation in ...


FPGA :FFT Core in Xilinx

Started by bijoy in comp.arch.fpga14 years ago 4 replies

Hi Any body used FFT core given by coregenerator in Xilinx ? Does it work as they said in their data sheet.. regards bijoy

Hi Any body used FFT core given by coregenerator in Xilinx ? Does it work as they said in their data sheet.. regards bijoy


FFT core

Started by Grumps in comp.arch.fpga12 years ago 11 replies

[posted to comp.arch.fpga + comp.lang.vhdl] Hi All I've had a quote from a 3rd party to develop a floating point FFT core for us (1Mpt)....

[posted to comp.arch.fpga + comp.lang.vhdl] Hi All I've had a quote from a 3rd party to develop a floating point FFT core for us (1Mpt). Probably for a Xilinx Virtex5 SXT. Obviously I'd like to get some more quotes, but would like to know if you have any recommendations? Thanks.


FFT implementation in Xilinx Spartan 3 started kit

Started by biot in comp.arch.fpga14 years ago 7 replies

Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-3 starter kit. I would...

Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-3 starter kit. I would like to know how many months it will take me to fully design it. As a novice i would like to know few suggestions and references for my project. I need help. I don't know from where to start.


FFT IP ALTERA FORMAT

Started by Anonymous in comp.arch.fpga13 years ago

Hello, Do you know what is the format of the FFT IP 2.2.1 Altera Output ? It's not compliant with IEEE 754 floating point format I think...

Hello, Do you know what is the format of the FFT IP 2.2.1 Altera Output ? It's not compliant with IEEE 754 floating point format I think that it have the exponent in 2's complement The mantissa in 2's complement with the MSB the bit sign Thanks for help


Coregen help

Started by Vivek Menon in comp.arch.fpga13 years ago 6 replies

Hi all, I am using the FFT coregen block with pipelined streaming option in my design implementation on a Virtex-4 FPGA. I am having a lot of...

Hi all, I am using the FFT coregen block with pipelined streaming option in my design implementation on a Virtex-4 FPGA. I am having a lot of issues with the implementation and have shortlisted them below: 1. First of all, the HDL generated file for FFT core 3.2 is not synthesizable. Is there any way to synthesize this block. I am using Xilinx ISE 7.1.4i and latest IP update. 2. I went back...


FFT module with Virtex-4 xc4vlx15

Started by Vivek Menon in comp.arch.fpga13 years ago

Hi, I am having problems synthesizing the fft module generated for Virtex-4 xc4vlx15. The files generated are only for simulation....

Hi, I am having problems synthesizing the fft module generated for Virtex-4 xc4vlx15. The files generated are only for simulation. Any suggestions?? Vivek


Host driver

Started by KingCharles in comp.arch.fpga11 years ago 1 reply

Hi all , I am a newbie of FPGA. So in the development chain I miss the following step: Suppose I have developed and tested my VHDL code,...

Hi all , I am a newbie of FPGA. So in the development chain I miss the following step: Suppose I have developed and tested my VHDL code, example an FFT. How can set a parameter (i.e FFT dimension) inside the VHDL code from the HOST PC? I need a driver. In which way this dirver have to be developed ? Thanks in advance


Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)

Started by Jhoberg in comp.arch.fpga12 years ago

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these...

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these are: http://www.altera.com/support/examples/verilog/verilog.html * Achieving Unity Gain in IFFT+FFT Pair Using Block Floating Point Arithmetic * Fast Fourier Transform (FFT) With 32K-Point Transform Length * Coefficient Reload Finite Impulse Response (FIR) Filter * Discrete Cosine Transform (DCT...


fixed FFT point implementation woes

Started by Anonymous in comp.arch.fpga11 years ago 3 replies
FFT

Hi, I am trying to create a mex file that does fixed point FFT (512 point?). I am generally ok with creating a C code in single precision to...

Hi, I am trying to create a mex file that does fixed point FFT (512 point?). I am generally ok with creating a C code in single precision to compute the the result and have ensured that it works fine as i get the correct result. (i read it back and plotted it in matlab.) the problem comes in when i try to convert it to fixed point. My input data is 24 bits integer. In addition, I take...


Implementation of 1024 point FFT in Actel FPGA

Started by cisivakumar in comp.arch.fpga14 years ago 3 replies

Hai, I want to do the main project as Implementation of 1024 point FFT in Actel FPGA.I have to find a new frequency identification...

Hai, I want to do the main project as Implementation of 1024 point FFT in Actel FPGA.I have to find a new frequency identification algorithm other than Fast Fourier Transform.Please give valuable notes,codes and suggestions for successully completing this project. Thanking you. I.Sivakumar


How to direct download to SRAM on Xilinx Spartan3?

Started by Riccardo Fregonese in comp.arch.fpga15 years ago 1 reply

Hello, I'm Ricky, an Italian student in eln eng. I'm working with a Xilinx Spartan3, I've designed a project that calculate a 12bit fft. The...

Hello, I'm Ricky, an Italian student in eln eng. I'm working with a Xilinx Spartan3, I've designed a project that calculate a 12bit fft. The core reads data (in serial mode) from the ISSI 1M RAM block, calculates the fft, and then writes the results in an other zone of the memory. My problem is to put the initial data into the memory (from my pc) and read them at the end, to verify if the ff...


Re: Verifying/comparing the FFT output between Xilinx Coregen block and Matlabís fft function

Started by Brian Drummond in comp.arch.fpga9 years ago 1 reply

On Thu, 3 Jun 2010 13:19:18 -0700 (PDT), Vivek Menon wrote: > Alan: > > Thanks for these tips. > > 2. Look for being off by an...

On Thu, 3 Jun 2010 13:19:18 -0700 (PDT), Vivek Menon wrote: > Alan: > > Thanks for these tips. > > 2. Look for being off by an output stride permutation or transpose. > I am not sure how to check this. Can you elaborate ? You started quite well, in your previous post. You observed: > ?xk_re[0] 117467 Matlab:f2_r[0] 117467 and > But on closer observati


fft in fpga using polar form

Started by Anonymous in comp.arch.fpga7 years ago 2 replies
FFT

i understand that representing large number of twiddle factors that are req= uired in a fft with large number of points is an issue when using...

i understand that representing large number of twiddle factors that are req= uired in a fft with large number of points is an issue when using fixed poi= nt scheme. To my understanding (which could be very wrong as i am new to th= is),the issue is large dynamic range that is needed to represent real and i= maginary parts of the complex numbers. Would the use of polar form to repre= sent them ...


FFT in VHDL (or Verilog) Tutorial

Started by Student (confused) in comp.arch.fpga13 years ago 2 replies

Hello, Can someone point me to simple implementation of FFT in VHDL(or Verilog) with testbench and good step-by-step description. I...

Hello, Can someone point me to simple implementation of FFT in VHDL(or Verilog) with testbench and good step-by-step description. I have implementation from Xilinx (which I will eventually use for hardware implementation), but I find it rather confusing (lack of vhdl experience). Algorithm used, # of points, Radix#, bit precision do not matter, as I'm looking for tutorial-like implementati...