FFT on an FPGA

Started by Anonymous in comp.arch.fpga14 years ago 3 replies
FFT

Q: I'm making a FFT block in hardware (on an FPGA) and I need some advice on multipliers: 1. I have made a simple (Fixed point arithmetic)...

Q: I'm making a FFT block in hardware (on an FPGA) and I need some advice on multipliers: 1. I have made a simple (Fixed point arithmetic) Radix-2 Decimation-in-time butterfly block which takes in two 16-bit complex inputs and another 16-bit input twiddle factor input and produces two complex outputs. Now with any standard multiplier circuit, multiplying N bits by N bits gives 2N bit produ...


Multiply Accumulate FPGA/DSP

Started by bart in comp.arch.fpga14 years ago 15 replies

I have been tasked with trying to implement a FFT algorithm in a FPGA/DSP architecture. The algorithm would be a N point FFT with...

I have been tasked with trying to implement a FFT algorithm in a FPGA/DSP architecture. The algorithm would be a N point FFT with 1000 frequency bins. Each frequency bin would require a multiply, by the constant e^jx, and then accumulate every 1 microsecond. This turns out to be 1000 multiply accumulates happening in parallel every 1 microsecond. Does anyone have experience doing somethin...


Xilinx FFT C-sim model

Started by Pete in comp.arch.fpga11 years ago 2 replies

I've noticed that the Xilinx FFT bit-accurate c simulation calls are very very slow. Anyone else notice this? I am working on hybrid...

I've noticed that the Xilinx FFT bit-accurate c simulation calls are very very slow. Anyone else notice this? I am working on hybrid fixed/floating-point digital signal processing application, and I frequently make calls to the bit-accurate simulation function (anywhere on the order of 1,000 times, to 1,000,000 times per run). As I'm attempting to run longer simulations, the runtime is b...


Is there a simple complex magnitude algorithm in FPGA implementation?

Started by SunLei in comp.arch.fpga13 years ago 9 replies
FFT

The FFT result output, implemented in a FPGA, is a complex number with 16-bit real part and 16-bit imaginary part. In the application, I only...

The FFT result output, implemented in a FPGA, is a complex number with 16-bit real part and 16-bit imaginary part. In the application, I only care about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there is an approximate estimation about this operation. and even more, the decibel algorithm. I think the decibel algorithm can be easily implemented by a looking-up-table sche...


What is value of scale_sch for FFT5.0 IP core for IFFT

Started by varun_agr in comp.arch.fpga8 years ago

We are using scaling in FFT5.0 IP Core for 64 transform size,radix 2 burst mode,natural order,scaling(so get same o/p size as i/p size),...

We are using scaling in FFT5.0 IP Core for 64 transform size,radix 2 burst mode,natural order,scaling(so get same o/p size as i/p size), i/p data 8 bit and expected o/p data also 8 bit. For this we scale for FFT in FFT5.0 IP CORE using trial method and using scale_sch="010101010101" in this case no overflow and for scale_sch="010101010100" it is overflow But when we give o/p of FFT to I/p of ...


Xilinx FFT core -- Is varying precision through the core possible?

Started by onkars in comp.arch.fpga9 years ago 1 reply

Hi, Can I set the XIlinx FFT core such that the early (maybe first 5 out of 10) stages use smaller precision bits (same as input precision)...

Hi, Can I set the XIlinx FFT core such that the early (maybe first 5 out of 10) stages use smaller precision bits (same as input precision) --- and they use scaling. But the later 5 stages don't use scaling --- instead we allow them more precision bits. This will help me to use less precision (and hence less hardware) with scaling wherever possible. (using the small precision throughout ...


fixed point fft butterfly stage testing help

Started by Anonymous in comp.arch.fpga7 years ago

I am new to verilog/hardware arithmetic and seeking good advice on testing a fft butterfly stage that I have written. module butterfly...

I am new to verilog/hardware arithmetic and seeking good advice on testing a fft butterfly stage that I have written. module butterfly #(parameter size=16, Q=4) (input signed[size-1:0] a_real, input signed[size-1:0] a_imag, input signed[size-1:0] b_real, input signed[size-1:0] b_imag, input signed[size-1:0] w_real, input signed[size-1:0] w_imag, output reg signed[size-1:0]...


ISE DDR Memory Controller to write between RAM and FPGA

Started by akco...@gmail.com in comp.arch.fpga13 years ago 4 replies

I need help on how to use the EDK DDR memory controller in ISE to write to/from ram and fpga directly. I have implemented the FFT provided...

I need help on how to use the EDK DDR memory controller in ISE to write to/from ram and fpga directly. I have implemented the FFT provided by Xilinx Coregen but need a faster memory controller to streamline the FFT process rather than the EDK-PowerPC DDR controller in C that is provided. Any help is appreciated. Thanks Ashwin


FFT : XK_INDEX

Started by little_orange in comp.arch.fpga13 years ago
FFT

From the wave, I find the start,rfd,busy,edone,done and the dv are the same as the datesheet shown, but the xk_index is wrong, it just shows...

From the wave, I find the start,rfd,busy,edone,done and the dv are the same as the datesheet shown, but the xk_index is wrong, it just shows 0,64,128,192,256....,960,why? where are the other values? Who has ever met this problem?I would appreciate your help very much.


Fast Fourier Transform

Started by Sander Odekerken in comp.arch.fpga16 years ago 1 reply

Hi, At school we have a project and our subject is to make a simple spectrum analyser. Now I want to know if it would be possible to perform a...

Hi, At school we have a project and our subject is to make a simple spectrum analyser. Now I want to know if it would be possible to perform a realtime FFT with an FPGA/CPLD (if possible in Xilinx). And if it is possible, where I can find/download the source and which chip is best to use. Any help will be appreciated. Thanks in advance, Sander Odekerken


Meaning of output value?

Started by Sander Odekerken in comp.arch.fpga15 years ago 2 replies

Hello everybody, For a school project I use the Xilinx Coregen FFT core. It does work, but what does the output mean? Is the Real output the...

Hello everybody, For a school project I use the Xilinx Coregen FFT core. It does work, but what does the output mean? Is the Real output the amplitude and the Imaginary output the phase? If anyone knows, please HELP!!! thanks, Sander Odekerken


SoC benchmarks

Started by Vivek Menon in comp.arch.fpga10 years ago
FFT

I am looking for SoC benchmarks such as VOPD, FFT, MPEG4 for performance evaluation on FPGAs.

I am looking for SoC benchmarks such as VOPD, FFT, MPEG4 for performance evaluation on FPGAs.


DSP Library for PPC405?

Started by Anonymous in comp.arch.fpga13 years ago

I noticed that the PPC405 in the V4s has a MAC instruction. Does anyone know if there are optimized filter or fft routines to take advantage of...

I noticed that the PPC405 in the V4s has a MAC instruction. Does anyone know if there are optimized filter or fft routines to take advantage of this? I do my signal procesing in the FPGA but it would be nice to be able to do some simple procesing with the core. Thanks, Clark


pi/4 DQPSK demapping

Started by kyrten in comp.arch.fpga15 years ago

In a project at university, I'm using 2048 pt FFT core from Xilinx CoreGenerator and the output data are modulated with pi/4 DQPSK. What's the...

In a project at university, I'm using 2048 pt FFT core from Xilinx CoreGenerator and the output data are modulated with pi/4 DQPSK. What's the best way to demapping the symbols? Should I use comparators and decision boundary? Any info or papers related to this will help. Thanks in advance.


asic gate count

Started by vija...@gmail.com in comp.arch.fpga11 years ago 9 replies

hi, i have got xilinx fft IP core from coregen. Is there any way that i can get asic gate count for this ? Any help / hint is...

hi, i have got xilinx fft IP core from coregen. Is there any way that i can get asic gate count for this ? Any help / hint is greatly appreciated. thanks, vijayant.


What can I do if my chip can't meet timing?

Started by Student in comp.arch.fpga15 years ago 17 replies

Hi, there: My clock is 40MHz, but I have complicated FFT operations and other DSP stuff. The longest path is 25.8ns, though after I set the...

Hi, there: My clock is 40MHz, but I have complicated FFT operations and other DSP stuff. The longest path is 25.8ns, though after I set the constraints at 23ns...Previously it was 27.5ns at constraints of 25ns... What may I do now? How far can over constraining go? The source codes are from other people so I can't change a lot of it. Besides -opt_mode Speed in XST, what else control...


Calculating SFDR in FPGA

Started by Mile in comp.arch.fpga9 years ago 2 replies

Hello All, I am new in this forum. I would like to ask if there is a way to calculate the SFDR in FPGA. I have limited resources in the...

Hello All, I am new in this forum. I would like to ask if there is a way to calculate the SFDR in FPGA. I have limited resources in the FPGA, so calculating the FFT is not so preferable. knowing that my bandwidth is around 1.5 GHz. my main goal is to evaluate the ADC, SFDR specifically. any idea is appreciated. Mile --------------------------------------- ...


Chipscope

Started by Anonymous in comp.arch.fpga11 years ago 5 replies

Hi! We are students working on implementing FFT on FPGA, virtex 4. We used Chipscope to test our code and capture signals off the...

Hi! We are students working on implementing FFT on FPGA, virtex 4. We used Chipscope to test our code and capture signals off the hardware while its running. when we tried to test an 8 bit adder using chipscope, in the ILA core, we constantly got an error which said 'waiting for core to be armed'. We understand that this indicates that appropriate trigger signal has not been provided. We'v...


ANN: Tyd-IP Code Generator adds NCO design capability

Started by Anonymous in comp.arch.fpga13 years ago

Hi, In adition to filter and fft creation, Tyd-IP Code Generator now generates VHDL for NCO design. Demo may be downloaded from...

Hi, In adition to filter and fft creation, Tyd-IP Code Generator now generates VHDL for NCO design. Demo may be downloaded from website. http://www.tyder.com Bob


Tutorial for C based bit-accurate hardware modeling ?

Started by onkars in comp.arch.fpga9 years ago 4 replies
FFT

I am a student who is trying to model a parallel hardware architecture for FFT using a C. My aim is to verify the correctness of my architecture...

I am a student who is trying to model a parallel hardware architecture for FFT using a C. My aim is to verify the correctness of my architecture and also estimate the noise introduced when fixed point is used. Is there any tutorial/book or any help that can guide me in this process of C modelling --- and especially for fixed point models? Thank you. ------------------------...