Fast Fourirer Using Xilinx ISE

Started by Hari in comp.arch.fpga16 years ago

Hi, I have an automatically generated code from some source "cztgen.exe". I am working on performing FFT (C-Z Tfranform).The code basically...

Hi, I have an automatically generated code from some source "cztgen.exe". I am working on performing FFT (C-Z Tfranform).The code basically has filter (FIR)coefficient computation.I am using two other code to perform multiplication and store coefficient/twiddle factors(not that of filter). My problem is I am not getting write answers when i simulate the codes.The multiplier and coefficen...


FPGA Processor for Signal Processing ?

Started by Anonymous in comp.arch.fpga11 years ago 3 replies

You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Microblaze from firms...

You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Microblaze from firms like Xilinx. Are there also implementations of processors special designed for signal processing that realize things like FFT for example ? Thanks for help


[Newbie] Suitable FPGA for my project

Started by Franco Tiratore in comp.arch.fpga13 years ago 8 replies
FFT

Hi all. I'm a total newbie to FPGA programming, therefore I'm looking for suggestions. In my project I have the following specs (these are only...

Hi all. I'm a total newbie to FPGA programming, therefore I'm looking for suggestions. In my project I have the following specs (these are only the critical ones, the whole project consists of additional blocks): - 384 Mbit/s input bitrate - 64-point FFT block, complex numbers with 16 bit fixed-point precision for each real number, the calculation must be performed in less than 1us - 80 M...


Altera simulation models performance

Started by mikel in comp.arch.fpga11 years ago 2 replies

Hi Is there a way to increase performance of Altera functional simulation models? Specifically, I am using FFT core in our project and this...

Hi Is there a way to increase performance of Altera functional simulation models? Specifically, I am using FFT core in our project and this is the bottleneck of simulation speed, which I am not surprised to see, given that VHO model is hundred of thousand lines of technology mapped code consisting of Altera library primitives. Using Verilog *.VO does not give much improvement. Moreover, F...


about digilent board

Started by deadflower in comp.arch.fpga16 years ago 3 replies

Hi, group, I plan to buy digilent combo board DIO2 combo. Does anybody know if a download cable will be included in the package? also, do they...

Hi, group, I plan to buy digilent combo board DIO2 combo. Does anybody know if a download cable will be included in the package? also, do they provide the software like foundation or webpack? I plan to implement some work of dsp, like FFT, FILTER. Hope this spartan II (200k gates) FPGA on this board helps. Has anybody tried that on digilent's board either? Thanks!


how to implement Fast Fourier Transform on virtex pro

Started by aj in comp.arch.fpga14 years ago 2 replies

I am a student and a novicee for FFT... can any one tell me how to start with implementing Fast Fourier Transform on xilinx virtex pro. i know...

I am a student and a novicee for FFT... can any one tell me how to start with implementing Fast Fourier Transform on xilinx virtex pro. i know there xilinx core generator which can do... but i want to do it for floating point.... any help for this starter... would be highly appreciated... i am getting lots of info, but there is nothing that is convincing me... IF any one can tell me the ste...


Xcell Article on 1.2Gsamples/sec FFT

Started by Andrew FPGA in comp.arch.fpga12 years ago 3 replies

Hi all, Just read an interesting article in Xilinx's xcel publication. Lots of technical detail, and no "marketing" to speak...

Hi all, Just read an interesting article in Xilinx's xcel publication. Lots of technical detail, and no "marketing" to speak of. http://www.xilinx.com/publications/magazines/dsp_03/xc_pdf/p42-44-3dsp-andraka.pdf After reading this I had a couple of burning questions I'm wondering if anyone, or Ray himself, can shed some light on 1) 1.2 Gsamples/s seems like a pretty high input data rate - ...


Estimating number of FPGAs needed for an application

Started by Anonymous in comp.arch.fpga12 years ago 6 replies
FFT

Hi all I'm absolutely new to FPGAs, in fact my work is much more related with the SW than with the HW, so I need to solve a problem that...

Hi all I'm absolutely new to FPGAs, in fact my work is much more related with the SW than with the HW, so I need to solve a problem that ideally I was not targeted to. The issue is this: I have to estimate (roughly) the number of FPGAs needed to support a typical signal processing algorithm, steps are as follows, always in single-precision: 1.16k complex samples FFT 2. 16k complex ve...


ChipScope - impact on design or not?

Started by in comp.arch.fpga13 years ago 17 replies

I used to believe that ChipScope did not have any impact on the design. I used to. I have two FPGAs communicating on the PCB (LVDS). One of...

I used to believe that ChipScope did not have any impact on the design. I used to. I have two FPGAs communicating on the PCB (LVDS). One of them (called source here) is doing some signal processing and sends the result to the destination FPGA. If I probe (with ChipScope) some internal results of the processing (FFT output) in the source, the data looks fine at the destination. However...


security system password by voice recognition commands

Started by pemiliv in comp.arch.fpga11 years ago 2 replies

HI everyone, i'm starting in the world of DSP, i have a project its a security system by voice patter recognition, and i have used pic16f877a in...

HI everyone, i'm starting in the world of DSP, i have a project its a security system by voice patter recognition, and i have used pic16f877a in others projects, but it seems not enough for dsp, thou it has a ADC converter 10 bit - fmax = 20mhz, and i was thinking to combine with fpga spartan 3a (sending the digital signal to spartan and then maybe do some fft and filter processing ) ... but ...


Xilinx ISE and IP cores

Started by Nemesis in comp.arch.fpga14 years ago 7 replies

Hi everyone, I'm going to buy Xilinx ISE Foundation, I'd like to know if this package contains also IP cores like DDC, FFT and so on. It seems...

Hi everyone, I'm going to buy Xilinx ISE Foundation, I'd like to know if this package contains also IP cores like DDC, FFT and so on. It seems that the "LogiCore" IPs should be shipped within ISE Foundations, am I right? -- I do whatever the voices tell me to do. |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.org


Writing output signals to text file (VHDL)?

Started by Vitaliy in comp.arch.fpga13 years ago 9 replies

Hello, I am using FFT v3.2 core from Xilinx. I have Xilinx ISE/Model Sim. The outputs of the core are xk_re and xn_re. 1) I am expanding...

Hello, I am using FFT v3.2 core from Xilinx. I have Xilinx ISE/Model Sim. The outputs of the core are xk_re and xn_re. 1) I am expanding Xilinx-provided test bench file. I am trying to write the outputs to .out file. Below are the lines of the code I'm using for that. if (done='1' and busy='1') then i1


Integrating Atera =?UTF-8?B?4oCcRkZUIE1lZ2FDb3JlIEZ1bmN0aW9u4oCd?= =?UTF-8?B?IGluIE1lbnRvciBGUEdBIEFkdmFudGFnZSA3LjI=?=

Started by Friedrich Kiesel in comp.arch.fpga13 years ago

Hi, I want to use the Atera ?FFT MegaCore Function? in a Design created with Mentor FPGA Advantage 7.2. Importing the created Files in HDL...

Hi, I want to use the Atera ?FFT MegaCore Function? in a Design created with Mentor FPGA Advantage 7.2. Importing the created Files in HDL Designer is no Problem, but when I try to run Synthesis with the integrated Plugin ?Quartus II Synthesis Flow? Quartus shows this Error: Error (10481): VHDL Use Clause error at fft.vhd(35): design library "fft_lib" does not contain primary


how to know that SRL16 was infered on xilinx?

Started by onkars in comp.arch.fpga9 years ago 1 reply

Hello, I am implementing a core from xilinx (FFT) and wanted to know how the feedback shift registers are implemented. The xilinx core manual...

Hello, I am implementing a core from xilinx (FFT) and wanted to know how the feedback shift registers are implemented. The xilinx core manual says that the earlier stages that need large shift registers uses Block RAM and other stages use distributed RAM. Does this mean it used SRL16s? How do the SRL16s show up in the MAP report if they are being used? Do they show up under "Specific Featu...


FPGA-ASIC Migration

Started by Venkat in comp.arch.fpga11 years ago 4 replies

Hello all, I have a question regarding migration of design from Xilinx FPGA to ASIC. There are lot of Xilinx IP Cores(I am sure even Altera...

Hello all, I have a question regarding migration of design from Xilinx FPGA to ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have too) which are commonly used for Arithmetic Purposes. For instance my design uses the Xilinx FFT/IFFT IP Cores and if the design has to be moved to the ASIC at later stages, can Xilinx Provide the netlist for ASIC technology as well? I hop...


slice # change from .syr to map report

Started by charles in comp.arch.fpga15 years ago 1 reply

I was experimenting a coregen generated FFT module. How come the slice utilization jump 6 fold from the synthesis report to map report? XST...

I was experimenting a coregen generated FFT module. How come the slice utilization jump 6 fold from the synthesis report to map report? XST does not just synthesis the logic into generic logics, it synthesize the logic to target resources, right? What I am saying is that if I change the target device, the # of slice used would change if the architecture of the slice is different between the...


Altera FPGA and data from matlab workspace.

Started by Anonymous in comp.arch.fpga11 years ago 2 replies

Hey, I need to send some data to the Altera Stratix II FPGA board from the matlab workspace and then do some FFT, FIR process on that and...

Hey, I need to send some data to the Altera Stratix II FPGA board from the matlab workspace and then do some FFT, FIR process on that and then return the data from the FPGA back into the matlab workspace. How do I do that? Kindly let me know if there is some tutorial which is Altera specific on this which can tell me how to do it step by step. Thanks and Regards, Jayaram


Block RAM

Started by Basuki Endah Priyanto in comp.arch.fpga16 years ago 1 reply

Hello all, I am working on FFT and instead of using Xilinx Block RAM, I write the = memory block using VHDL codes. However, after compiling...

Hello all, I am working on FFT and instead of using Xilinx Block RAM, I write the = memory block using VHDL codes. However, after compiling and = synthesizing, it seems like they are occupying the Xilinx FPGA slices. = Thus, it occupies a lot of CLB/gates. Is there any such away that the memory is written in our own vhdl code = but it occupies the memory allocation (Block RAM) in FPGA ? ...


How to add customer peripheral with IP core to EDK?

Started by FPGA in comp.arch.fpga12 years ago 1 reply

Hi All, I am trying to add a customized OPB peripheral to the Microblaze system in EDK/Platform Studio 8.1. My peripheral uses a FFT...

Hi All, I am trying to add a customized OPB peripheral to the Microblaze system in EDK/Platform Studio 8.1. My peripheral uses a FFT core generated from Core Generator so it only comes with ngc netlist. I instantiate the core in the user_logic.v. And I was able to synthesize the peripheral using generated ISE project file by adding the IP source file (core wizard) to the project. But whe...


Open source Core generators?

Started by recoder in comp.arch.fpga11 years ago 1 reply
FFT

Dear All, Are there any Open source Core generators available? I am looking for FIR and FFT Core generators but also wonder if open...

Dear All, Are there any Open source Core generators available? I am looking for FIR and FFT Core generators but also wonder if open source generators for other functions exist. Thanks in Advance