Hi all, I need a 16 words deep FIFO. I'm using the Xilinx FIFO Generator Core. I chosen an asynchronous FIFO, but I found an odd behaviour. The...

Hi all, I need a 16 words deep FIFO. I'm using the Xilinx FIFO Generator Core. I chosen an asynchronous FIFO, but I found an odd behaviour. The FIFO stores only 15 words then the Full Flag goes high. Is it normal? Why isn't it storing 16 words? I tried to monitor the number of words in the FIFO so I added the RD_DATA_COUNT and WR_DATA_COUNT outputs, they should 4 bits wide but instead the...

Hi all, I am exploring the possibility of using a FIFO between the OPB and my custom IP-core. I want to write data from my IP into the FIFO. I...

Hi all, I am exploring the possibility of using a FIFO between the OPB and my custom IP-core. I want to write data from my IP into the FIFO. I see that the FIFO has an output called RFIFO2IP_WrAck. This is an ackonowledge signal that the fifo asserts when it is ready to read data. According to some examples it seems like this signal can go low randomly, that means regardless of the fifo being f...

Hi, I'm designing a itu656 video data format decoder, where I need use a FIFO to send the active pixel to the next module for processing. ...

Hi, I'm designing a itu656 video data format decoder, where I need use a FIFO to send the active pixel to the next module for processing. But, as you known, I'm a newbie in EDA field. I can't say what kind of FIFO will be useful in this design and I don't know how to use the xilinx FIFO ip core. Anybody has a project like this? Can you give me a application note of how to use th...

Hi, A part of my project needs the FPGA spartan3 ( XC3S100) to be interfaced with the USB via FIFO. I made the FIFO using logic core's FIFO...

Hi, A part of my project needs the FPGA spartan3 ( XC3S100) to be interfaced with the USB via FIFO. I made the FIFO using logic core's FIFO generator v 2.3. I am intending to make a asynchronous FIFO. The FIFO has full, almost full, read , write signals. Would XEM3010 be the right choice for it? Please advice! Regards John

Hi, I'm using EDK 10.1 with SP3 and ISE 10.1 with SP3 I generated a FIFO in ISE to use it in an EDK design. It is a 64 bit wide and 512...

Hi, I'm using EDK 10.1 with SP3 and ISE 10.1 with SP3 I generated a FIFO in ISE to use it in an EDK design. It is a 64 bit wide and 512 deep FIFO. The fifo is created and implemented as ngc. The simulation show the behaviour as expected, but in the actual implementation in the FPGA it looks like the FIFO is full of zeros after reset. After all zeros are read out of the fifo normal behav...

Hallo to Al i use Virtex2pro and edk 6.3i,ise 6.3 I have a problem with the read fifo. I created the fifo with ed wizard and its a part of...

Hallo to Al i use Virtex2pro and edk 6.3i,ise 6.3 I have a problem with the read fifo. I created the fifo with ed wizard and its a part of IPIF. When you see the vhdl code belove write in the FIFO(4 Register depth and 32 Bit wide) 4 datas 1,3,5,7 But when i read the registers with the software, i get only datas and 7. The Datas between get not the fifo Perhaphs had any the same proble...

Hi, I generated two FIFOs using Xilinx ISE CoreGen. Both FIFOs are 64-bit wide, but one FIFO depth is 16, the other is 64. After doing...

Hi, I generated two FIFOs using Xilinx ISE CoreGen. Both FIFOs are 64-bit wide, but one FIFO depth is 16, the other is 64. After doing the mapping, I was surprised to find that both FIFOs use the same amount of BlockRam. I cannot understand the reason since the 16-depth FIFO will definately use less memory than the 64-depth FIFO. Please give some idea about this. Thanks.

I use ise9.1 and synplify8.4.2,I use the core generator to generate a fifo,the parameters as follow,different clock and different data...

I use ise9.1 and synplify8.4.2,I use the core generator to generate a fifo,the parameters as follow,different clock and different data bus widths,write 16 bits and read 128 bits,now I want to use the fifo data counts to control my logic,the fifo depths is 256 for read,and I don't use the all fifo,if the fifo data conter reach 200,the logic must stop writing,the logic can't write one more or l...

I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL) a dual clock FIFO (a FIFO with different read and write clock). The...

I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL) a dual clock FIFO (a FIFO with different read and write clock). The problem is that the Atmel macro-generator has the ability to generate only single clock FIFO. Is it possible that Atmel did not think to include the possibility of creating dual clock FIFO's in an efficient way??? Have I to design a FIFO by myself with ...

I have to make a quick fix to get OPB_UARTLITE fifo larger seems like simple thing, just replace the fifo, but xilinx coregen is not able to...

I have to make a quick fix to get OPB_UARTLITE fifo larger seems like simple thing, just replace the fifo, but xilinx coregen is not able to create a FIFO with first word fall-through so there latency on read and data from uart seems like delayed. the FIFO has to use BRAM, I was hoping that coregen is easy way but it doesnt look like. sure its not so complicated to write it from scratch bu...

Hello Groups, I have a 1Gbps SERDES output from the Network processor. But as i have 2 SERDES signal coming from the back plane, depending of...

Hello Groups, I have a 1Gbps SERDES output from the Network processor. But as i have 2 SERDES signal coming from the back plane, depending of SEL line i have to connect one of the SERDES to network processor. So i am using FPGA to interface this, which takes a SERDES input and I have FIFO for transmit FIFO, recieve FIFO and FIFO controller and this FIFO is again connected to another SERDES...

Note: using EDk 8.2.02 with peripheral generated with the wizard with FIFO enabled and one user interrupt that is set to the fifo_almostfull...

Note: using EDk 8.2.02 with peripheral generated with the wizard with FIFO enabled and one user interrupt that is set to the fifo_almostfull line. I'm set up to generate interrupts on the fifo almost full signal but I get a couple interrupts and then it stops. If I go read the occupancy register I get a number(0x737) greater than the size of the fifo (0x400). If I then go and manually read ...

It is my first time here, so hello everybody! :) I have problems with Xilinx FIFO on Spartan 3. As far as I understand it, standard FIFO sends...

It is my first time here, so hello everybody! :) I have problems with Xilinx FIFO on Spartan 3. As far as I understand it, standard FIFO sends data out in the next clock cycle after I set 'rd_en' signal to '1'. In my case I get output not in the next, but in the second clock cycle. Do you know what may cause that problem? Here is what I do (first I put in FIFO two byte words): STATE1 => if

I have tried to instantiate the Asynchronous FIFO core (v6) from Coregen, and it's been giving me trouble. First, I can't get it to produce a...

I have tried to instantiate the Asynchronous FIFO core (v6) from Coregen, and it's been giving me trouble. First, I can't get it to produce a FIFO using distributed RAM (I wanted a 31-deep FIFO). When I try, it tells me there is a block RAM in the usage summary. If I try to open the core again after it's generated, it sometimes just beeps and exits (no error messages at all), sometimes i...

Hi, I have tried to synthesize the synchronous fifo example "FIFO.vhd" from Ben Cohen's book "Real Chip Design and Verification Using...

Hi, I have tried to synthesize the synchronous fifo example "FIFO.vhd" from Ben Cohen's book "Real Chip Design and Verification Using Verilog and VHDL" on a Lattice EC15 (Synplicity compiler) For the FIFO registers declaration I add the following attribute : attribute syn_ramstyle : string; attribute syn_ramstyle OF FIFO_r : SIGNAL IS "block_ram"; And yet the sy...

Hello Given two values, compare_value and change_value, is it possible to simultaneously update all values within a fifo that...

Hello Given two values, compare_value and change_value, is it possible to simultaneously update all values within a fifo that equal compare_value to change_value without having to devote a number of clock cycles proportional to the depth of the fifo? The memory storage need not be a fifo, but that is how it should function when reading and writing to it. Also, a value will only be pulle...

Hi! I have a big FIFO chip covered by dust, that I'd like to finally use. The most useful application I'm imagining for it is to finally...

Hi! I have a big FIFO chip covered by dust, that I'd like to finally use. The most useful application I'm imagining for it is to finally make myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU) is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought. What I'm asking you is: should I connect the probes (just a header cable) directly to the FIFO, or should I use ...

hi all; I am using Edk to create IP peripheral which contains RD and WR Fifos. My question is, if the required data to be written to the...

hi all; I am using Edk to create IP peripheral which contains RD and WR Fifos. My question is, if the required data to be written to the read fifo is undefined it will not be stored in the fifo or what. fatma

i want to read & write data to/from a fifo placed in fpga. MCU's external bus is connected to the chip. I am using the sync-fifo ip...

i want to read & write data to/from a fifo placed in fpga. MCU's external bus is connected to the chip. I am using the sync-fifo ip of Altera CycloneII. The data bus and control signal are connected to fifo directly. it's unfortune that when i read once from bus, data would be read twice from fifo because there are two clock rising edges during read signal(low active) is resetted. I think...

Hello, I am having the following code for FIFO. When I try to synthesize the verilog code on ISE targetting BRAM it throws following...

Hello, I am having the following code for FIFO. When I try to synthesize the verilog code on ISE targetting BRAM it throws following warning: INFO:Xst:1788 - Unable to map block on BRAM. Output FF does not have same control signals as . Can anyone help me to resolve this problem? Thanks! Code:: module fifo(write_enb,read_enb, data_in, data_