Smallest GPL UART

Started by Giuseppe Marullo in comp.arch.fpga6 years ago 28 replies

Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still confused about what are my...

Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still confused about what are my options. I would go with micro UART by Jeung Joon Lee but I am unable to determine its license. There are others, like osvudu by Timothy Goddard seems released under (a) MIT license, thus compatible with GPL. I need very simple stuff: baud...


practical experience with GPL IP core in commercial product

Started by Anonymous in comp.arch.fpga3 years ago 50 replies

I was wondering if anybody has had practical experience using IP licensed with the GNU Public License (GPL, not LGPL) within a commercial FPGA...

I was wondering if anybody has had practical experience using IP licensed with the GNU Public License (GPL, not LGPL) within a commercial FPGA development. I found some Verilog under GPL I would like to use; attempts to contact the author have gone unanswered (abandonware?). I can't find a 3rd party with a comparable commercial IP offering, so "plan B" is rolling my own (four weeks labor?). ...


The Java processor JOP is now GPL

Started by Martin Schoeberl in comp.arch.fpga10 years ago
GPL

Hi all, it has been silent about JOP in this group for a while. However, development is still very active. I've now decided to put the...

Hi all, it has been silent about JOP in this group for a while. However, development is still very active. I've now decided to put the project under GPL v3. For those who don't know the project: JOP is an implementation of the Java virtual machine in hardware - that means a Java processor. It's not the only Java processor in the world, but now the first one under GPL ;-) If you want ...


Soft IPs licensing

Started by hata in comp.arch.fpga12 years ago 2 replies
GPL

Hi all, I am looking for information about licensing of HW designs. To be more specific I would like to find out what kind of license comes...

Hi all, I am looking for information about licensing of HW designs. To be more specific I would like to find out what kind of license comes with the WishBone specification (rev B.3). I read on the OpenCores web site that they refer to the GPL licence but after having read it on http://www.gnu.org I have a lot of questions. It is not clear to me once a GPL licensed softcore is included in a...


Lattice "Open IP" license is GPL-compatible?

Started by Anonymous in comp.arch.fpga11 years ago 4 replies

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze...

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze or the lattice semi micro8. However, I'm worried about licensing issues, as I'd also like to be able to use the opencores IP and release the whole thing under the GPL. Does anyone know / have a strong opinion on whether or not the Lattice Open IP li...


Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm

Started by fjh-...@galois.com in comp.arch.fpga12 years ago

johannes.vanderhorst writes: > But it can be tricky applying the GPL to an HDL project, because > traditional concepts like source code and...

johannes.vanderhorst writes: > But it can be tricky applying the GPL to an HDL project, because > traditional concepts like source code and binary executables are > transferred to a domain with source, several intermediate netlist > formats, some of which can be regarded as source when you're wide > awake... The GPL defines what source code means: | The source code for a work means t


Xilinx ISE 7.1

Started by Eric in comp.arch.fpga13 years ago 1 reply

I just got my copy of ISE 7.1 and noticed that I now have to click through both the GPL and the LGPL before installing... I don't remember having...

I just got my copy of ISE 7.1 and noticed that I now have to click through both the GPL and the LGPL before installing... I don't remember having to do this before -- does anyone know what changed or was added? ...Eric


logic analyzer for Spartan3 starterkit, GPL VHDL and java based sw

Started by Antti Lukats in comp.arch.fpga11 years ago 2 replies

http://www.sump.org/projects/analyzer/ (link info with thanks to Carsten) Antti

http://www.sump.org/projects/analyzer/ (link info with thanks to Carsten) Antti


nios2 toolchain sources...

Started by Jedi in comp.arch.fpga12 years ago 8 replies
GPL

Evening... The NIOS2 sources are only available on the shipped CD's..right? So...then the downloadble NIOS2 evaluation version breaks the...

Evening... The NIOS2 sources are only available on the shipped CD's..right? So...then the downloadble NIOS2 evaluation version breaks the GPL since it only contains gcc/binutils binaries? rick


wishbone

Started by Alessandro Basili in comp.arch.fpga8 years ago 6 replies
GPL

Hi everyone, I'm just about to start an implementation of an open spacewire IP core (still trying to understand under which license, GPL, LGPL,...

Hi everyone, I'm just about to start an implementation of an open spacewire IP core (still trying to understand under which license, GPL, LGPL, CeCILL...) and I was wondering whether is a good idea to have a wishbone interface implemented. I am pretty new to SoC bus and even though google is "one of my best friends" I still didn't get the feeling how popular it is and how spread it is ...


LEON processor core

Started by Martin Schoeberl in comp.arch.fpga12 years ago 10 replies

I'm wondering why there are so few messages about LEON [1] in this group. LEON looks like a very solid design (used by the ESA) and it is...

I'm wondering why there are so few messages about LEON [1] in this group. LEON looks like a very solid design (used by the ESA) and it is available in a GPL version. Could be a vendor independent replacement of NIOS/MicroBlaze with a path to an ASIC. The configuration is done via a simple Tcl/Tk script and the Makefile contains several targets. Works out-of-the-box for available tragets. Ad...


Which Simulators

Started by gallen in comp.arch.fpga13 years ago 7 replies

I'm sure this kind of things has come up in the past, but given that things change, I'd like to throw this out there. Which simulators do...

I'm sure this kind of things has come up in the past, but given that things change, I'd like to throw this out there. Which simulators do people like to use for their HDL purposes? I have tried a couple of simulators and I was curious about peoples recommendations. I have used Modelsim XE starter for my purposes (I am just a hobbyest now), icarus verilog and GPL cver. I have used the ...


Xilinx USB Blaster FX2 firmware and CPLD replacement under GPL released

Started by Antti in comp.arch.fpga11 years ago 3 replies

http://inisyn.org/src/xup/ its already done! I was kind of hoping someone does it, and voila, done... and as a good smile bonus, I really...

http://inisyn.org/src/xup/ its already done! I was kind of hoping someone does it, and voila, done... and as a good smile bonus, I really like that webpage, the author can really name thing with proper names. to understand that just place the cursor over "proprietary nightmare" - and you see the hyperlink - www.jungo.com !! :) nice way to say it: "The windriver stuff really is one m...


M*Blaze in Cyclone ! End of What? ;)

Started by Antti Lukats in comp.arch.fpga13 years ago 4 replies

Hi I would like to quote Martin Schoeberl: "And a MB on an Altera FPGA, that's the end of the world." Well the end of the world must then...

Hi I would like to quote Martin Schoeberl: "And a MB on an Altera FPGA, that's the end of the world." Well the end of the world must then be TODAY? MB is working in Cyclone FPGA, screenshots available: http://uclinux.openchip.org/forum/viewtopic.php?t=11 some comments - the program that is running in the FPGA is compiled using GPL GNU toolchain so there can be no legal issues with t...


Linux capable free/GPL SOFT CPU for XC3S500E?

Started by Wojciech Zabolotny in comp.arch.fpga10 years ago 11 replies

Hi All, I'm looking for a possibility to run Linux (may be a ucLinux) on a XC3S500E containing CPU and some custom peripherials. The hardware...

Hi All, I'm looking for a possibility to run Linux (may be a ucLinux) on a XC3S500E containing CPU and some custom peripherials. The hardware platform should be a Spartan3E Starter Kit (rev. D), or something like this. I have found the almost ready to use solution here: http://muranaka.info/pukiwiki/index.php?MicroBlaze%20uClinux%20and%20Spartan-3E%20Starter%20Kit but it is MicroBlaze ...


small, free simple state machine processor suggestions?

Started by Anonymous in comp.arch.fpga11 years ago 5 replies

Has anyone found or could recommend a small(ish) processor for more complex state machine tasks that is: 1. ~1000 LUTs or so (smaller is...

Has anyone found or could recommend a small(ish) processor for more complex state machine tasks that is: 1. ~1000 LUTs or so (smaller is better) 2. available under a free license (say, GPL, LPGL, BSD) 3. available in vhdl? Ideally something like picoblaze would probably do what I want, except that it's not under any of the available licenses, and pacoblaze is vhdl (and potentially an IP...


opencores.org - Question on project licensing?

Started by Pacbell User in comp.arch.fpga14 years ago 6 replies

I would like to contribute a multi-cycle (slow, but area-compact) (Hehe, someone else already released a pipelined integer-divider, to the...

I would like to contribute a multi-cycle (slow, but area-compact) (Hehe, someone else already released a pipelined integer-divider, to the opencores.org repository. Gence I'm marketing my divider as 'compact'!) I am reading through the FAQ, and one part has me a bit confused... === The 'licensing' portion -- I understand that the 'GPL' license is fairly restrictive in that it forces de...


picoblaze IDE for Linux

Started by M6 in comp.arch.fpga12 years ago 5 replies

I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM). The IDE is an open-source project (GPL-license) and works under the Linux...

I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM). The IDE is an open-source project (GPL-license) and works under the Linux operating system. The IDE supports the following: - Editor with syntax highlighting, - Assemble and export to: HEX, VHDL or MEM files, - Simulate the source code and see/modify the scratchpad, registers and I/O ports. For those who are intereste...


LatticeMico32 extremly poor performance without caches

Started by Antti in comp.arch.fpga11 years ago 18 replies

Hi just some results for LatticeMico32: * no cache * code and data in Block RAMs testing with software loop sw r0,r0,0x100 bri...

Hi just some results for LatticeMico32: * no cache * code and data in Block RAMs testing with software loop sw r0,r0,0x100 bri -1 this loop executes in 28 system clock cycles! simulation done with Xilinx ISE built-in simulator ISIM, using coregen for addsub and block RAM components. Antti PS as much as I see Lattice is at time of writing violating GPL license or does anyo...


Gaisler on a Spartan 3E Starter Kit?

Started by David M. Palmer in comp.arch.fpga11 years ago 6 replies

Gaisler has a nice suite of GPL'd IP for an AMBA-bussed Leon3 (SPARC) system with Ethernet, DDR RAM, Spacewire, PCI, AES Crypto, and others. ...

Gaisler has a nice suite of GPL'd IP for an AMBA-bussed Leon3 (SPARC) system with Ethernet, DDR RAM, Spacewire, PCI, AES Crypto, and others. http://www.gaisler.com There is a nice configuration program that lets you select the modules you want. However, the configuration program etc. has to be configured to tell it the details of the board, what PHY and RAM it has, and you need a .uc...