does ISE 6.3 improve timing vs. ISE 6.2 ?

Started by Nahum Barnea in comp.arch.fpga13 years ago 1 reply
ISE

Hi. I am using ISE 6.2 for xc2vp30,-6 that compiles for 100 MHz. Now I am trying to stretch the design to 133 MHz. Can anyone compare the...

Hi. I am using ISE 6.2 for xc2vp30,-6 that compiles for 100 MHz. Now I am trying to stretch the design to 133 MHz. Can anyone compare the performance improvement of ISE 6.3 vs. ISE 6.2 (if any) ? THANKX


problem with ISE versions

Started by nezhate in comp.arch.fpga11 years ago 5 replies

Hi all, I want to use a small cricuit (written in verilog and was designed using ISE 3) in an other project using ISE 8.1. the problem is that...

Hi all, I want to use a small cricuit (written in verilog and was designed using ISE 3) in an other project using ISE 8.1. the problem is that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is an error. why this occur ?


ISE 6.2i strange behavior

Started by sjulhes in comp.arch.fpga12 years ago 3 replies

Hi ! I installed ISE and EDK 6.2i with SP3, and ISE as a stange behavior. When I go through steps synthesis, P&R and .bit generation every...

Hi ! I installed ISE and EDK 6.2i with SP3, and ISE as a stange behavior. When I go through steps synthesis, P&R and .bit generation every thing is ok. If I launch impact or if I swap to another windows application and back to ISE, all green marks go back to ? and ISE launches the wholel flow !!!! It is a big waste of time ! Does anyone has a clue ? Just one point, there was a ISE 6....


ISE BaseX customers

Started by in comp.arch.fpga11 years ago 3 replies

I read from the file http://www.xilinx.com/company/press/kits/ise81i/8_1i_faq.pdf the following: --BEGIN-- 14. What happened to the ISE...

I read from the file http://www.xilinx.com/company/press/kits/ise81i/8_1i_faq.pdf the following: --BEGIN-- 14. What happened to the ISE BaseX configuration? .... skipped text .... All in-maintenance ISE BaseX customers are receiving a copy of ISE Foundation at no extra cost with the ISE 8.1i release. --END-- I'm an in maintenance BaseX customer. Does it mean that I can get full ISE f...


ISE 7.1 small advice about project files (.ISE extension)

Started by Antti Lukats in comp.arch.fpga12 years ago 3 replies

Hi just a little thing: starting from 7.1 ISE abondoned the use of plain text project files, the new project files with .ISE extension are...

Hi just a little thing: starting from 7.1 ISE abondoned the use of plain text project files, the new project files with .ISE extension are PKZIP compressed - that can cause an additional problem if ISE is not closed correctly as the ZIP archive could corrupted rendering it totally useless, ISE will refuse to open and use it. And there is no recovery, the project must be done from scratch -...


Ise foundation and Ise Webpack

Started by Pablo in comp.arch.fpga10 years ago 1 reply

Hi, does anyone know the difference between Ise Foundation and Ise Webpack?. I have Ise Webpack installed in my PC and now I have some software...

Hi, does anyone know the difference between Ise Foundation and Ise Webpack?. I have Ise Webpack installed in my PC and now I have some software which needs Ise Foundation and I don`t know if there is some difference. Although I have to install Xilinx System Generator. Is it on Ise Foundation? Is another module of Xilinx? Is free? Regards, Pablo


Using EDK libraries in ISE

Started by Harish in comp.arch.fpga13 years ago 2 replies

Hello all, How can we simulate the EDK IP cores in ISE? I created a new project in ISE and copied the vhdl files that comes with EDK onto a...

Hello all, How can we simulate the EDK IP cores in ISE? I created a new project in ISE and copied the vhdl files that comes with EDK onto a new file and tried to synthesize it. However the synthesis failed as the library referred to in the design was not seen by ISE. Can anyone tell me how to overcome this? Thanks


edn macro in ISE

Started by Yaseen Zaidi in comp.arch.fpga12 years ago 1 reply

I like to use a Xilinx written macro (edn) in my design using ISE 6.3. I seems ISE does not accept edn file. I could not find any documentation...

I like to use a Xilinx written macro (edn) in my design using ISE 6.3. I seems ISE does not accept edn file. I could not find any documentation on using edn netlist for ISE. It follows the macro is little old and older foundation had provision where edn elements could be instantiated. However, I like to do this for ISE. The edn is synthesized and optimized netlist. Where in ISE design flow I ...


ISE does not initialize the bitstream of a EDK project

Started by Francis in comp.arch.fpga12 years ago 2 replies

I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I had to import ISE to ...

I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I had to import ISE to EDK and do update bitstream so that it works on my FPGA board. Looks like EDK does it correctly and not ISE. I also tried to use my project in ISE with an export to ProjNav with the EDK tool. Same thing I had to import my ISE project to EDK to ini...


ISE does not initialize the bitstream of a EDK project

Started by Francis St-Pierre in comp.arch.fpga12 years ago 2 replies

I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I had to import ISE to ...

I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I had to import ISE to EDK and do update bitstream so that it works on my FPGA board. Looks like EDK does it correctly and not ISE. I also tried to use my project in ISE with an export to ProjNav with the EDK tool. Same thing I had to import my ISE project to EDK to ini...


How to move project files from ISE 7.1 to ISE 10.1

Started by Anonymous in comp.arch.fpga9 years ago 7 replies

Hello Guys, I am trying to move a current project files that contain PCI Xilinx IP Cores from ISE 7.1 to ISE 10.1. What it is the best way to...

Hello Guys, I am trying to move a current project files that contain PCI Xilinx IP Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the project. The ISE 7.x does not have "export source" function. Also, I have tried to move the following files: (.v , .xco and .ucf) and have created a new project with the same target and same name in ISE 10.1 and started adding the source fil...


Using a different editor for ISE 5

Started by Theron Hicks in comp.arch.fpga14 years ago 1 reply

Hello, Is there a way that I can (within ISE 5) use a different editor? I want the editor to be integrated into the ISE system but I want...

Hello, Is there a way that I can (within ISE 5) use a different editor? I want the editor to be integrated into the ISE system but I want to use a different editor. The feature that I most want is automatic formating of indents, etc. ISE does a good job, but if I screw up when I put in a new block of code I want to add auto-indent (like that available in Matlab). Folks at Xilinx.... T...


xilinx ise 8.1 mig 1.4 /1.5

Started by guy in comp.arch.fpga11 years ago

hello the ise7.1 had the mig1.4 for memory interface generator does it work on the ise 8.1? if not is there any newer version for ise...

hello the ise7.1 had the mig1.4 for memory interface generator does it work on the ise 8.1? if not is there any newer version for ise 8.1? thanks guy


Using EDK libraries in ISE

Started by Harish in comp.arch.fpga13 years ago

Hello all, How can we simulate the EDK IP cores in ISE? I created a new project in ISE and copied the vhdl files that comes with EDK onto a...

Hello all, How can we simulate the EDK IP cores in ISE? I created a new project in ISE and copied the vhdl files that comes with EDK onto a new file and tried to synthesize it. However the synthesis failed as the library referred to in the design was not seen by ISE. I'm trying to synthesize an OPB ZBT controller. Can anyone tell me how to overcome this? Thanks


How to open an ISE 8.1 project in ISE 7.1?

Started by Rainier in comp.arch.fpga11 years ago 6 replies

I want to open an ISE 8.1 project in ISE 7.1, but it seems impossible. and there's even no compatibility property in the save option. My...

I want to open an ISE 8.1 project in ISE 7.1, but it seems impossible. and there's even no compatibility property in the save option. My project has verilog, vhdl, schematic and coregen files. thanks.


Nondeterministic ISE Placement

Started by Tom in comp.arch.fpga12 years ago 1 reply
ISE

I remember a few years ago we would have to run ISE PAR several times in order to meet timing. One we had a decent layout, we would lock...

I remember a few years ago we would have to run ISE PAR several times in order to meet timing. One we had a decent layout, we would lock it down because of the chance of never being able to reproduce it. Does ISE still suffer nondeterministic placement? Also, how much has ISE PAR improved since 5.1/6.1? -Tom


Install two version of EDK/ISE (8.1, 8.2) in my windows xp?

Started by Pablo in comp.arch.fpga10 years ago 5 replies

Is it possible to install two diferent versions of EDK/ISE, that is, one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the first...

Is it possible to install two diferent versions of EDK/ISE, that is, one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the first one for simulink, but my custom board uses the second one (for the drivers). I suppose that the problem is the "Path Variable". Has anyone some experience in this?. I will post my results as soon as possible. Regards, Pablo


Last ISE version that supports XC95xxXL ?

Started by Antti in comp.arch.fpga11 years ago 8 replies

Hi can someone suggest what version of ISE would be best candidate not to fail on XC95xxXL fitting? ISE 8.2SP3 fails badly - I was hoping...

Hi can someone suggest what version of ISE would be best candidate not to fail on XC95xxXL fitting? ISE 8.2SP3 fails badly - I was hoping not have to install older versions and check with WebFitter, but: "WebFITTER has been replaced by ISE WebPACK" !!!! and latest ISE fails badly with XC95xxXL as target, the same VHDL design reports different number of pins being used if XC95xxXL is ...


most stable version of ISE ?

Started by Mike Harrison in comp.arch.fpga6 years ago 3 replies

I've seen lots of messages a while ago about how ISE is going downhill... Which version of ISE would people recommend for fairly simple VHDL...

I've seen lots of messages a while ago about how ISE is going downhill... Which version of ISE would people recommend for fairly simple VHDL projects using Spartan-3 and Spartan-6? I'm currently developing with an old S3A prototype board, with a view to change to S6 for the next iteration. I've used ISE 10.1 in the past with no issues, but would prefer to upgrade now to ease any pain chan...


going backwards, Xilinx ISE 7.1 to ISE 6.3

Started by Rob Young in comp.arch.fpga12 years ago 1 reply

I own and use Xilinx ISE 7.1 BaseX and to develop Spartan-3 code. I have a client who owns and uses ISE 6.3 BaseX but is not in a position to...

I own and use Xilinx ISE 7.1 BaseX and to develop Spartan-3 code. I have a client who owns and uses ISE 6.3 BaseX but is not in a position to upgrade to 7.1 right now, policy against changing tools until a project has been completed. Anyway, I have developed some VHDL code that makes use of the filter and FIFO IPs from CoreGen and I'd like to just turn it over to them so they can int...