ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)

Started by Alfmyk in comp.arch.fpga11 years ago 3 replies

Hi all. I have created a simple application to test ISRs. This application is very similar to the application example provided by xilinx with...

Hi all. I have created a simple application to test ISRs. This application is very similar to the application example provided by xilinx with EDK 8.2 for ISR testing: there is a timer and UART ISR.Press f key leds "blink" faster, while pressing s leds "blink" slower. This application works fine if loaded directly in BRAM. If I decide to create the application to be loaded in RAM(so setting ....


uBlaze ISR : Steps to write/implement an ISR...

Started by Alfmyk in comp.arch.fpga11 years ago 2 replies
ISR

Hi all. At the moment I never implement a ISR on uBlaze system. I have seen, I know I have to use the INTC IP driver routines, but I have...

Hi all. At the moment I never implement a ISR on uBlaze system. I have seen, I know I have to use the INTC IP driver routines, but I have seen also there are some commands in uBlaze interface Header. For example: microblaze_enable_interrupts(void); microblaze_disable_interrupts(void); I imagine before of all I HAVE to use microblaze_enable_interrupts(void); that it has priority and wor...


Xiic with low lvl interrupts

Started by simax in comp.arch.fpga9 years ago 1 reply

Hello everybody ... Im trying to code an isr for the xiic Ip from Xilinx EDK. I did everything like tht documentation says but it wont...

Hello everybody ... Im trying to code an isr for the xiic Ip from Xilinx EDK. I did everything like tht documentation says but it wont work. i get an interrupt when the modul is adressed as slave and its the AAS irq. After i get it, ill reset the interrupt that it is acknowledged but it wont work .. thats how my isr looks like ... void iic_1_handler(void * baseaddr_p) { XGpio...


Nios stops responding to interrupts

Started by tns1 in comp.arch.fpga13 years ago 6 replies

QuartusII 4.0 SP1, SOPC builder with Nios 3.2, Cyclone C4. I have the Nios32 @ 30mhz working fine with my user logic modules, but any ISR I...

QuartusII 4.0 SP1, SOPC builder with Nios 3.2, Cyclone C4. I have the Nios32 @ 30mhz working fine with my user logic modules, but any ISR I try works a random number of times (1 to 30 times?) and then stops getting called. By bringing out some internal signals to pins, I can see that the irq signal from my module is asserted, but the ISR just does not get called. This is the first tim...


Nios II interrupt

Started by Frank van Eijkelenburg in comp.arch.fpga11 years ago 1 reply

Hi, I am new to the Nios II core. I have built a simple system with a timer which is set as periodically timer. I have registered an...

Hi, I am new to the Nios II core. I have built a simple system with a timer which is set as periodically timer. I have registered an interrupt service routine: alt_irq_disable(TIMER_0_IRQ); res = alt_irq_register(TIMER_0_IRQ, NULL, timer_isr); With this code I still come in my installed ISR. So registering is also enable the interrupt. Is that correct, is there a way to reg...


Lattice Mico32 Simulation in Modelsim

Started by Anonymous in comp.arch.fpga1 year ago 4 replies

Hi, I have written a Mico32 application in C. Now I want to simulate my Mico32 system in the Modelsim simulator including the C...

Hi, I have written a Mico32 application in C. Now I want to simulate my Mico32 system in the Modelsim simulator including the C application (toggling some LEDs, ISR for controling 7 SEGMENT display). As I have found out (by reading the Mico32 HW/SW handbook) I can create a memory initialization file which is 148MByte after generation. For that I have used the Mico32 Software Deployment Too...


XSpi_Transfer within interrupt context

Started by Thomas Taranowski in comp.arch.fpga5 years ago 1 reply

I'm using the standalone bsp for a ppc440 on a Virtex 5. I have a scenario where I have to read from an external chip over spi in response to...

I'm using the standalone bsp for a ppc440 on a Virtex 5. I have a scenario where I have to read from an external chip over spi in response to a gpio interrupt. The issue I run into is that when I call XSpi_Transfer from within the context of the gpio isr, the call just hangs, presumably dues to the fact that the xspi_l portion of the driver is attempting to use interrupts to service it's f...


OPB write actions

Started by Frank in comp.arch.fpga14 years ago 3 replies

Hi, I've succesfully build a microblaze system with external interrupt and my own IP core (using the opb slave template in the EDK). The...

Hi, I've succesfully build a microblaze system with external interrupt and my own IP core (using the opb slave template in the EDK). The interrupt is connected to a dip-switch. In the ISR I'm writing some data to my own IP core (which is an OPB slave). My OPB slave is reading some other dip-switches and put the result to some LEDs (yes I'm using an evaluation board ;). So far everything is...


virtex II pro - own core on plb with 2 interrupts

Started by SvenA in comp.arch.fpga10 years ago 1 reply

Hi, I'am trying to set up an Interface for an A/D - D/A Codec on an virtex II pro plattform using the (ppc) plb bus. What i want is to connect...

Hi, I'am trying to set up an Interface for an A/D - D/A Codec on an virtex II pro plattform using the (ppc) plb bus. What i want is to connect two interrupt pins from this A/D codec to an INT-Controller. Is it possible to it this way, without using the intterupt support implemented in the ipif-interface. I don't want to do a polling onto one of the isr-flags in the ipif- interupt controller....


Multiple Interrupt handling in XPS 8.2i

Started by moon in comp.arch.fpga8 years ago 1 reply

Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the...

Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the two interrupts.These interrupts pins are input to the interrupt controller INTC (1.00 c). Initially both interrupts are disabled.Then only high priority interrupt is enabled. What my objective is that when a high priority interrupt occurs:in its ISR it should ...


usb transfer between PC and de2 board

Started by summer in comp.arch.fpga8 years ago

hi everyone, I need to transfer 16 bytes data block (a packet of 16 bytes data) from PC to DE2 board and then the DE2 board will send the data...

hi everyone, I need to transfer 16 bytes data block (a packet of 16 bytes data) from PC to DE2 board and then the DE2 board will send the data back to PC. I?m use the firmware of device controller of isp1362 chip on de2 board to transfer the data. below is one part of my codings: (this is the coding from interrupt service routine,ISR.c) void Isr_Ep02Done(void) { unsigned char bbuf[16]