JTAG Opcodes for Altera MAX7000S

Started by Patrik in comp.arch.fpga14 years ago 3 replies

Hi, I try to program a JTAG chain with a MAX7064S and a MAX7032S via JTAG with a microcontroller. The problem is, that I couldn't find the...

Hi, I try to program a JTAG chain with a MAX7064S and a MAX7032S via JTAG with a microcontroller. The problem is, that I couldn't find the JTAG opcodes for ISP. Is there any documentation about it? Thanks, Patrik


PC to JTAG

Started by Matthew Hicks in comp.arch.fpga10 years ago 1 reply

I read all of the documents I could find about using the JTAG port as a communications interface to the FPGA and implemented my own JTAG...

I read all of the documents I could find about using the JTAG port as a communications interface to the FPGA and implemented my own JTAG controlled logic. The problem is, none of the documents that I read gave a decent solution as to how to get access to the JTAG chain on the PC side of things. I am using the Virtex II-Pro XUP board which has a USB front end to the JTAG interface. Is ...


Is there any compatibility difference between The parallel JTAG PC4 and JTAG III??

Started by jack lalo in comp.arch.fpga13 years ago 1 reply

Hi all, I'm asking if there is any difference between the Xilinx JTAG III and IV??? I saw that the speed of the second is 8 time quicker...

Hi all, I'm asking if there is any difference between the Xilinx JTAG III and IV??? I saw that the speed of the second is 8 time quicker than the first, but i need a JTAG cable and all the schematics are for the old one. Is it matter if i use the JTAG III instead of the PC4??? thanks


S3ESK JTAG

Started by Guru in comp.arch.fpga11 years ago

Hi all, Did anyone try to use the Spartan3 Starter Kit (S3ESK) as a USB JTAG programmer? I want to connect the Virtex4 MiniModule (2.5V JTAG)...

Hi all, Did anyone try to use the Spartan3 Starter Kit (S3ESK) as a USB JTAG programmer? I want to connect the Virtex4 MiniModule (2.5V JTAG) to the 3.3V S3ESK JTAG port. I tried to with some resistor dividers to accomodate voltage (100 & 330ohm) and TDO & TDI swapped, but the connection was not very sucesfull. Any ideas? Guru


cyclone jtag

Started by Jedi in comp.arch.fpga13 years ago

Has anybody tried to use the "cyclone_jtag" module in his design? So I could access registers through JTAG in my design... I know that I can...

Has anybody tried to use the "cyclone_jtag" module in his design? So I could access registers through JTAG in my design... I know that I can use opencores jtag module but I want to use the existing JTAG port. rick


JTAG Prog. and Power Requirments

Started by Drew in comp.arch.fpga13 years ago

Hello, I am programming EPM3064ALC44-7 using JTAG-ByteBlaster. I will use the exact circuit shown in Figure 2 of application note AN-95 from...

Hello, I am programming EPM3064ALC44-7 using JTAG-ByteBlaster. I will use the exact circuit shown in Figure 2 of application note AN-95 from Altera which describes connections to JTAG header and will also supply power to device through, VCCIO and VCCINT pins (3.3 Volts). However, I am trying to make a prototype board, which will only program devices using JTAG header (might seem crazy, b...


V5 JTAG download weirdness

Started by Anonymous in comp.arch.fpga9 years ago 3 replies

Has anyone out there sucessfully brought up a V5 download chain ( LX50 w/SPI serial master, four LX30 slaves) over JTAG using 10.1i SP3 ? ...

Has anyone out there sucessfully brought up a V5 download chain ( LX50 w/SPI serial master, four LX30 slaves) over JTAG using 10.1i SP3 ? I'm bringing up my first V5 board design, and I'm seeing issues that are reminiscent of older software and JTAG startup bugs of years past; searching the Answer Records didn't turn anything up specifically for V5. The JTAG chain itself seems quite ...


JTAG pin states

Started by Anonymous in comp.arch.fpga14 years ago 2 replies

Hi All, I'm building a JTAG chain demultiplexer so I can control 30 identical JTAG chains from a single point. Can anyone confirm the...

Hi All, I'm building a JTAG chain demultiplexer so I can control 30 identical JTAG chains from a single point. Can anyone confirm the quiescent (not doing anything) states of the JTAG pins; so I know what to hold the pin levels at when a chain is not being used. I see that TMS, TCK & TDI have internal pull-ups, so would I place a logical 1 on these when they're not in use? TDO is easy e...


SystemACE and Jtag

Started by Scarex in comp.arch.fpga13 years ago 2 replies

I'm working on a Xilinx demonstration board equipped with a jtag chain including a SystemACE CF and a Virtex-II FPGA. My goal is to configure...

I'm working on a Xilinx demonstration board equipped with a jtag chain including a SystemACE CF and a Virtex-II FPGA. My goal is to configure the FPGA via Jtag bypassing the SystemACE. Unfortunaly, after the hardware reset, the SystemACE is configured by default to look for a bitstream on the Compact Flash: in this way, it doesn't allow me to reach the FPGA through the Jtag. I have to use...


JTAG tutorial

Started by Jean Nicolle in comp.arch.fpga12 years ago 7 replies

I created a small tutorial about JTAG. See http://www.fpga4fun.com/JTAG.html I'd be happy to hear about mistakes/suggestions. Thanks.

I created a small tutorial about JTAG. See http://www.fpga4fun.com/JTAG.html I'd be happy to hear about mistakes/suggestions. Thanks.


Programming the JTAG flash in circuit

Started by wpim...@aol.com in comp.arch.fpga12 years ago 3 replies

We have a Xilinx Flash (XCF series I believe) that we would like to program in circuit from a microcontroller in order to support...

We have a Xilinx Flash (XCF series I believe) that we would like to program in circuit from a microcontroller in order to support field reconfigurability. This flash has a JTAG backend. We were thinking about using the GPIO ports on a microcontroller to wiggle the JTAG lines and load the new files that way. Problem is we don't know much about the upper protocol involved in JTAG and the doc...


Spartan-3e JTAG no device id

Started by Alan Nishioka in comp.arch.fpga10 years ago 22 replies

I am trying to get an xc3s250e-4tq144c to configure using JTAG. 1. impact reads 0x00000000 as idcode This causes impact to error out...

I am trying to get an xc3s250e-4tq144c to configure using JTAG. 1. impact reads 0x00000000 as idcode This causes impact to error out during identify with a strange error about missing bsdl's 2. JTAG works using impact debug mode. I can put it in bypass and also see the length of the instruction register. I can see data shifting in and out so I know JTAG works. 3. Part markings are: ...


JTAG program failed

Started by mughat in comp.arch.fpga12 years ago 1 reply

I have problems programming my EEPROM through JTAG. Most of the times it fails but I have succeeded once. When programming the FPGA directly it...

I have problems programming my EEPROM through JTAG. Most of the times it fails but I have succeeded once. When programming the FPGA directly it works all the time. I am using JTAG Cable Model IJC-2 from Insight The EEPROM is a Xilinx XCF08P The FPGA is a Xilinx Spartan 3 1500K gates What can i try to correct this problem? Is it possible to turn down the speed of the JTAG clock? Than...


Chipscope 7.1 and JTAG TAP

Started by Paul in comp.arch.fpga10 years ago 3 replies

Hi I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a Instruction width of 6 bits. I have a design for which I had...

Hi I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a Instruction width of 6 bits. I have a design for which I had automatically generated a JTAG Controller. I can successfully sythesize the design as well as the JTAG TAP. The problem is just that when I use ChipScope Pro with to connect to the device it tells me that there are 0 Core units found in the JTAG device chain. ...


JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable

Started by Fred in comp.arch.fpga11 years ago 6 replies

Does anyone know of any software, ideally freeware, which can use the above JTAG interfaces to exercise other JTAG interfaces on non FPGA...

Does anyone know of any software, ideally freeware, which can use the above JTAG interfaces to exercise other JTAG interfaces on non FPGA devices? In my case I'd like to read the state of pins on an unrelated device.


reprogram xcf08 serial prom without jtag

Started by Anonymous in comp.arch.fpga11 years ago 1 reply

All, Does anyone know if there is an easy way to reprogram xilinx xcf08 serial proms outside of tying the jtag lines to the chip and emulating...

All, Does anyone know if there is an easy way to reprogram xilinx xcf08 serial proms outside of tying the jtag lines to the chip and emulating the whole jtag protocol? Has anyone used jtag successfully to reprogram these proms from the FPGA that they load? Thanks, Clark


Tiny JTAG connector

Started by Eric in comp.arch.fpga9 years ago 8 replies

What do "real" engineers do when they want to preserve the ability to connect a JTAG pod to a device, but board layout/space concerns prevent...

What do "real" engineers do when they want to preserve the ability to connect a JTAG pod to a device, but board layout/space concerns prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG header that's common on all the JTAG Products? I'm somewhat envisioning a tiny small-pin-count press-to-fit connector, but I have no idea. Are there any standards in this area? Thanks! ...


ANN: Low cost & high speed JTAG interface

Started by www.amontec.com in comp.arch.fpga13 years ago

Hi all, "Save your debug time using Raven JTAG interface" Raven JTAG interface is 5x faster than the popular Wiggler emulator. "Save your...

Hi all, "Save your debug time using Raven JTAG interface" Raven JTAG interface is 5x faster than the popular Wiggler emulator. "Save your money using Chameleon POD" Amontec company provides a Raven JTAG interface solution for only EUR159.- . Coming with - Multi-ICE adapter - USB Power JTAG connector - FREE Chameleon POD programmer (can be downloadable on http://www.amontec.com/down...


JTAG Connection For PPC Using VisonProbe V2PRO V2P30

Started by Marc R in comp.arch.fpga13 years ago

I am having trouble getting the JTAG chain to validate with my Windriver Vision probe (using Vison Click software). It is on seperate PPC JTAG...

I am having trouble getting the JTAG chain to validate with my Windriver Vision probe (using Vison Click software). It is on seperate PPC JTAG I/O: TCK, TDI, TMS, TDO, not using TRST or HALT. This is seperate from the FPGA dedicated JTAG pins. I am using the v2p30 and only one proc. The other proc is not instantiated, the documentation indicates several ways to hook this up. Does anyone ha...


Problem with JTAG server on Quartus 4.0 for XP

Started by Steven Derrien in comp.arch.fpga13 years ago

Hello, I'am trying to use Quartus II and NIOS II sdk for teaching and I'm facing a problem with the JTAG server service on the XP machines...

Hello, I'am trying to use Quartus II and NIOS II sdk for teaching and I'm facing a problem with the JTAG server service on the XP machines that are used by our students. Whenever a user logs in the JTAG server service systematically fails to launch automatically and reports an "error code 0". The only way to make sure the JTAG service is launched correctly is to log in as an admini...