ISE, JTAG and ChipScopePro.

Started by Massimo Gaggero in comp.arch.fpga17 years ago 2 replies

Hallo to everybody, I bought a "Spartan 3 Starter Kit" and to program the board there's a JTAG cable. I've two questions: Can I use the...

Hallo to everybody, I bought a "Spartan 3 Starter Kit" and to program the board there's a JTAG cable. I've two questions: Can I use the same cable to do In Circuit Debugging with JTAG System? Do I need some software not bundled with Xilinx ISE to do it? Thanks, Massimo.


JTAG program failed

Started by mughat in comp.arch.fpga16 years ago 1 reply

I have problems programming my EEPROM through JTAG. Most of the times it fails but I have succeeded once. When programming the FPGA directly it...

I have problems programming my EEPROM through JTAG. Most of the times it fails but I have succeeded once. When programming the FPGA directly it works all the time. I am using JTAG Cable Model IJC-2 from Insight The EEPROM is a Xilinx XCF08P The FPGA is a Xilinx Spartan 3 1500K gates What can i try to correct this problem? Is it possible to turn down the speed of the JTAG clock? Than...


JTAG + PROM error!

Started by Anonymous in comp.arch.fpga14 years ago 7 replies

Hi, I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V Master-Serial...

Hi, I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V Master-Serial Configuration with 3.3V and JTAG with Platform Flash Prom" as here: http://www.xilinx.com/support/answers/20477.htm. To reduce the sources of error, I disconnected the JTAG input signals TMS, TCK, TDO to the FPGA, and connected the TDO directly from the PROM t...


JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable

Started by Fred in comp.arch.fpga16 years ago 6 replies

Does anyone know of any software, ideally freeware, which can use the above JTAG interfaces to exercise other JTAG interfaces on non FPGA...

Does anyone know of any software, ideally freeware, which can use the above JTAG interfaces to exercise other JTAG interfaces on non FPGA devices? In my case I'd like to read the state of pins on an unrelated device.


burn xcf16p through PCI jtag

Started by Anonymous in comp.arch.fpga17 years ago

Hi, I developed PCI board with xilinx prom & fpga on it. Since PCI has jtag pins and since the prom xcf16p is programmed through its jtag...

Hi, I developed PCI board with xilinx prom & fpga on it. Since PCI has jtag pins and since the prom xcf16p is programmed through its jtag interfacce, I wonder if there is a known application software to burn the xilinx prom & devices through PCI jtag interface ? THANKX NAHUM


reprogram xcf08 serial prom without jtag

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

All, Does anyone know if there is an easy way to reprogram xilinx xcf08 serial proms outside of tying the jtag lines to the chip and emulating...

All, Does anyone know if there is an easy way to reprogram xilinx xcf08 serial proms outside of tying the jtag lines to the chip and emulating the whole jtag protocol? Has anyone used jtag successfully to reprogram these proms from the FPGA that they load? Thanks, Clark


JTAG programing specs for XC18V01 PROM

Started by barnhart in comp.arch.fpga16 years ago 6 replies

Would anyone know where to get the JTAG programming specs (and programming times, page sizes, etc) for the XC18V01? I'd like to create an...

Would anyone know where to get the JTAG programming specs (and programming times, page sizes, etc) for the XC18V01? I'd like to create an application for re-programming a 18V01 that takes as input the Intel Hex (MCS) and outputs JTAG bit banging. Xilinx recommends (app note 58 and 500) generating SVF or XSVF and using the XSVF player for the JTAG bit-bang. Unfortunately the memory require...


opendous-jtag support for independent USB drivers for JTAG/Impact/Chipscope?

Started by wzab in comp.arch.fpga10 years ago

Hi, Probably most Linux users working with Xilinx tools use the excellent drivers written by Michael Gernoth and available at...

Hi, Probably most Linux users working with Xilinx tools use the excellent drivers written by Michael Gernoth and available at http://rmdir.de/~michael/xilinx/ I'm looking for a way to embed the whole USB JTAG converter into device, so design should cheap and efficient. Last time I started to use them with FT2232H chip connected directly to the JTAG pins of FPGA. The result were acce


Problem with JTAG server on Quartus 4.0 for XP

Started by Steven Derrien in comp.arch.fpga17 years ago

Hello, I'am trying to use Quartus II and NIOS II sdk for teaching and I'm facing a problem with the JTAG server service on the XP machines...

Hello, I'am trying to use Quartus II and NIOS II sdk for teaching and I'm facing a problem with the JTAG server service on the XP machines that are used by our students. Whenever a user logs in the JTAG server service systematically fails to launch automatically and reports an "error code 0". The only way to make sure the JTAG service is launched correctly is to log in as an admini...


JTAG fundamentals question

Started by Silver in comp.arch.fpga15 years ago 3 replies

Hi everyone, I tried to figure this one out myself but it turns out not so easy for someone with this lack of experience like mine. I'm...

Hi everyone, I tried to figure this one out myself but it turns out not so easy for someone with this lack of experience like mine. I'm writing a PC app that will issue JTAG commands over paralell port to some unspecific FPGA at the moment, running let's say some cipher algorithm. I want to use my app to set input levels with JTAG and observe how it changes output signals. In order to...


SPROM JTAG confusion!

Started by Anonymous in comp.arch.fpga17 years ago 1 reply

Hello, I'm currently working on a project and I am at the stage where I'm ready to work on the PCB layout. For development I was using...

Hello, I'm currently working on a project and I am at the stage where I'm ready to work on the PCB layout. For development I was using the Digilent Spartan IIE development board (http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIEBoard.html) and would use the six pin JTAG connector with the Nuhorizons JTAG cable (http://www.nuhorizons.com/products/digilent/jtag-cabl...


Parallel JTAG cable on a USB-only W2K laptop?

Started by CF in comp.arch.fpga19 years ago 8 replies

Parallel JTAG cable on a USB-only W2K laptop? I am wondering if anyone has been able to successfully use a Xilinx parallel JTAG cable/adapter...

Parallel JTAG cable on a USB-only W2K laptop? I am wondering if anyone has been able to successfully use a Xilinx parallel JTAG cable/adapter with the ISE 5.2i iMPACT software to program EEPROMS (or even a successful boundary scan to see the JTAG chain) with a laptop that only has USB ports. I purchased an ECP mode bi-directional USB to Parallel IEEE 1284 converter cable to accomplish th...


Virtex 4 USER1 ~ USER4 JTAG commands

Started by Anonymous in comp.arch.fpga17 years ago 3 replies

Hello everyone, I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ USER4 JTAG commands from my software. I have used my...

Hello everyone, I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ USER4 JTAG commands from my software. I have used my software to access such USER1, USER2 commands in previous generation FPGAs such as Virtex-II. Virtex 4 uses different JTAG command bit patterns (10 bit long) and I changed the table so that JTAG commands to be issued have the correct JTAG command bit...


different JTAG programming cables

Started by David Fejes in comp.arch.fpga12 years ago 3 replies

Hello guys, is there any chance to get work a lattice jtag programming cable with xilinx products? I think, JTAG is a common standard, didn't?...

Hello guys, is there any chance to get work a lattice jtag programming cable with xilinx products? I think, JTAG is a common standard, didn't? I've a hw- usbn-2a lattice cable and I want use with xilinx cplds, but the iMAPCT doesn't find the cable. If this is not possible, can anyone suggest a webstore in Europe where I can order a xilinx JTAG cable? The digilent won't ship their progra...


newbie question about Xillinx JTAG cable

Started by Frank Schreiber in comp.arch.fpga16 years ago 1 reply

Hello guys, I have a JTAG cable with 1 line female output, but my board has only 2 lines- pins connector for JTAG. So, my question is how to...

Hello guys, I have a JTAG cable with 1 line female output, but my board has only 2 lines- pins connector for JTAG. So, my question is how to make ( or simpler to buy ) an adapter between them ? Thank you for reading. Greetings Frank


ByteblasterMV and QuartusII 3.0

Started by Christian Riesch in comp.arch.fpga19 years ago

I have a homebuilt Byteblaster MV which works fine with Altera Max+PlusII 10.2. With Quartus II 3.0 SP1 "Auto Detect" of the devices in the JTAG...

I have a homebuilt Byteblaster MV which works fine with Altera Max+PlusII 10.2. With Quartus II 3.0 SP1 "Auto Detect" of the devices in the JTAG chain works, but when I try to program it reports Info: Configuring device index 2 Error: Can't configure device. Expected JTAG ID code 0x110500DD for device 2, but found JTAG ID code 0x00000000. Error: Unexpected error in JTAG server -- error cod...


Done Pin Remains Low after JTAG Configuration of V2Pro

Started by Adarsh Kumar Jain in comp.arch.fpga18 years ago 5 replies

Hi, I am trying to configure V2P7s with JTAG, but after the iMPACT tool says programming succeeded, the done pin remains low and all the outputs...

Hi, I am trying to configure V2P7s with JTAG, but after the iMPACT tool says programming succeeded, the done pin remains low and all the outputs remain High. I have 8 V2P7s in parallel and they all the drive the same DONE line. What happens when we just program one of the 8 devices with JTAG in such a setup ? PLEASE HELP !!! Thanks in advance, Adarsh


Re: ChipScope Pro Loading Memory

Started by Guy Eschemann in comp.arch.fpga18 years ago 1 reply

I don't know of any ready-to-use solution for this, so I guess you will have to design your own. You could use a user-JTAG module in...

I don't know of any ready-to-use solution for this, so I guess you will have to design your own. You could use a user-JTAG module in your design (have a look at BSCAN_SPARTAN3 in the libraries guide). This will allow you get data in and out of your FPGA through the JTAG port. Then you will need a little logic to interface the JTAG module with your SRAM controller. On the PC side, you w...


PROM JTAG download cable for Xilinx Spartan II + Webpack

Started by ..:: Gabster ::.. in comp.arch.fpga19 years ago

Hi, I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm developing under Xilinx ISE 5. I'm wondering what would be the...

Hi, I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm developing under Xilinx ISE 5. I'm wondering what would be the simplest JTAG cable I could build (or buy if real cheap) to download my code in the PROM. Is any JTAG cable supposed to do the job? The fact is I already a very simple JTAG interface (with a 74HC244 buffer for parallel port)...I tried it but it didn'...


How to comm with Altera JTAG UART (from custom host software)?

Started by Kolja Waschk in comp.arch.fpga16 years ago 2 replies

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host PC? maybe via JTAG UART...

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host PC? maybe via JTAG UART etc... Would be nice if nios2-terminal provided a method to connect to the JTAG UART from own applications through Unix or TCP sockets, or something similar. Would be perfect if there was a public specification or source code example how to access ...