Implement a JTAG controller in an FPGA

Started by irish in comp.arch.fpga17 years ago 3 replies

Anyone done a JTAG controller in VHDL or Verilog? I want to use an FPGA to program another JTAG device. Cheers, Irish

Anyone done a JTAG controller in VHDL or Verilog? I want to use an FPGA to program another JTAG device. Cheers, Irish


JTAG port access in Cyclone

Started by Jedi in comp.arch.fpga17 years ago 12 replies

hello Is there any example of how to add JTAG port support into own non-SOPC builder design like I can directly access SPI config...

hello Is there any example of how to add JTAG port support into own non-SOPC builder design like I can directly access SPI config port? For example I want to read/set own register word from an own JTAG tool. thx rick


TRST Pin in Altera FPGAs

Started by erojr in comp.arch.fpga18 years ago 13 replies

The JTAG Standard defines a JTAG reset pin, TRST. This pin is little used. All Altera docs (Datasheets, ANs) define this pin but write nothing...

The JTAG Standard defines a JTAG reset pin, TRST. This pin is little used. All Altera docs (Datasheets, ANs) define this pin but write nothing about its usage. Therefore we did not connect it at all. But we experience problems in the JTAG chain: some EPC chips (especially big ones, like EPC8) almost never finish the Verification phase. I am wondering if this can be due to the unconnected...


data logging via JTAG?

Started by Anonymous in comp.arch.fpga17 years ago 2 replies

Hi. I have a simple board with an Spartan 3 FPGA and a AD connected to it. The board is configured via JTAG using the Xilix Platform Cable USB...

Hi. I have a simple board with an Spartan 3 FPGA and a AD connected to it. The board is configured via JTAG using the Xilix Platform Cable USB (24 Mhz). What I would like to do is to capture the data from the A/D converter to the computer via JTAG. Does anybody know of a good way to do this with the Xilinx applications (Chipscope, System Generator, etc)? Or maybe with a 3rd party tool? I ...


FPGAs and JTAG

Started by Adarsh Kumar Jain in comp.arch.fpga17 years ago

Hi All, I am stuck with some JTAG interconnection tests on a board with 9 Xilinx V2Pros and 2 Altera Stratixs. I am using JTAG Technologies...

Hi All, I am stuck with some JTAG interconnection tests on a board with 9 Xilinx V2Pros and 2 Altera Stratixs. I am using JTAG Technologies VIP Manager for the tests. Somehow the tool / software is getting into errors as it sees 1's on the GND net. I have digged into all possibilities as far as the software and test generation is concerned but am unable to find the source. Maybe the pr...


XCF02S + Spartan 2e JTAG config problems

Started by Gabor in comp.arch.fpga16 years ago 3 replies

I'm seeing some strange behavior when trying to program a Spartan 2e (XC2S150E) directly via JTAG. In the system it is normally programmed...

I'm seeing some strange behavior when trying to program a Spartan 2e (XC2S150E) directly via JTAG. In the system it is normally programmed using master serial mode from the XCF02S "platform flash" part. The JTAG chain starts with the XCF02S and then ends at the XC2S150E - no other parts. I can program the XCF02S without problem using JTAG. I can also program the XC2S150E without problem...


Readback Problems

Started by Sushmita in comp.arch.fpga18 years ago

Dear Sir, I have been trying to the contents of readback block ram on spartan II kit. This is how i tried I syntheized and implemented...

Dear Sir, I have been trying to the contents of readback block ram on spartan II kit. This is how i tried I syntheized and implemented the design using Jtag clk as start up clk and enableing the readback in configuartion option. then connnecting the jtag cable to the board . i tried to program using Jtag Programmer(Foundation Series 3.1). I clicked on the program in the Menu , it g...


JTAG issues Cyclone V SoC

Started by Al Clark in comp.arch.fpga8 years ago 3 replies

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog...

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog Devices' SHARC DSPs. I am working on the JTAG connection strategy. It seems to me that separate JTAG connections make more sense than chaining since Quartus may be running separately from the ARM (HPS). Unless someone tells me something diffe...


Looking for a USB JTAG cable

Started by Jason Thibodeau in comp.arch.fpga12 years ago 2 replies

Hello, I have a Spartan 3 Starter board. I used to program it with my parallel JTAG cable, but I now do my implementations on a laptop...

Hello, I have a Spartan 3 Starter board. I used to program it with my parallel JTAG cable, but I now do my implementations on a laptop without a parallel port. I am in the market for a USB JTAG cable. Requirements: Xilinx ISE 11.1 running on Fedora 12. Any suggestions? Will the digilent cable suffice? Thanks in advance. -- Jason Thibodeau www.jayt.org


xilinx JTAG

Started by Prakash in comp.arch.fpga16 years ago 3 replies

Hi, Iam trying to download opensource processor in xilinx dev. board XUPV2P. I'm not using any of the features like (Power PC/...

Hi, Iam trying to download opensource processor in xilinx dev. board XUPV2P. I'm not using any of the features like (Power PC/ controllers) which are inbuilt / xilinx prop. Now I've a doubt If suppose I configure my bit file thro' USB Jtag interface, should my logic (to be downloaded) contain the JTAG controller also, or the controller is hard coded in the chip. I get a warning while gene...


User I/O via Altera MAX7000S JTAG?

Started by Andrew Holme in comp.arch.fpga17 years ago 4 replies

Is there any way to use the JTAG pins of an EPM7128S for user I/O, without permanently commiting them as I/O and thereby losing the JTAG...

Is there any way to use the JTAG pins of an EPM7128S for user I/O, without permanently commiting them as I/O and thereby losing the JTAG capability? I want to download data from the PC, via a ByteBlaster cable, into a 2kx8 static RAM connected to the CPLD. I suppose I could add some jumpers for re-patching the 10-way header to standard I/O pins; or have a second, dedicated header for the RA...


Xilinx Sparta-3 configuration

Started by Aleco31 in comp.arch.fpga18 years ago

Hello, everybody! I have the following question regarding Xilinx Spartan-3 family. Can these devices, which require 2.5V to be connected to the...

Hello, everybody! I have the following question regarding Xilinx Spartan-3 family. Can these devices, which require 2.5V to be connected to the VCCAUX (JTAG and DLL power) be configured using former Parallel III cable, JTAG mode? Does it require some small series resistors on the JTAG signals as motioned it the SPARTAN-3 data sheet? Thanks a lot in advance. Alex Shrabstein.


Configurating multiple devices(FPGA and CPLD) with different Vccs through the JTAG

Started by john ong in comp.arch.fpga18 years ago 1 reply

Hi, I am new to configurating multiple devices through JTAG. Does anyone know if it is possible to configure multiple devices (Xilinx...

Hi, I am new to configurating multiple devices through JTAG. Does anyone know if it is possible to configure multiple devices (Xilinx Spartan FPGA and CPLD) in a daisy chain through JTAG. The problem I face is that the the devices concerned have different Vcc(s). The former is 5V and the latter is a 3.3V device. Is it only possible to configure them separately through JTAG. Thank you.


XC9500 JTAG Initialize problem

Started by Chelam in comp.arch.fpga16 years ago 3 replies

Hai XC9500 is not initialized and .log file directing me to look for hardware config problems. I have Connected Parallel cable and using JTAG...

Hai XC9500 is not initialized and .log file directing me to look for hardware config problems. I have Connected Parallel cable and using JTAG interface(assembled). All of JTAG Connections and VCC, GND connections were made properly The Part Iam tring to use :PLCC84-15. The software ( ISE3.3i) has been tried on both win-98 and Win-2000.Hardware working with Pentium IV processor. When ...


Jtag problem for Virtex II pro (XC2VP20-6FF896C).

Started by tripledirrble in comp.arch.fpga18 years ago 3 replies

I have a board using XC2VP20-6FF896c and two xc18v04 proms, seems Jtag have problem as: 1) Whenever there is a free-runnimg clock, the Jtag...

I have a board using XC2VP20-6FF896c and two xc18v04 proms, seems Jtag have problem as: 1) Whenever there is a free-runnimg clock, the Jtag config fails. when the free-runnimg clock is turned off, config successfully. 2) Maseter seral mode never work, check cclk, it is alway there. Could clock interference affect Jtag configuration? but I use the same design with virtex E, there is no...


[JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?

Started by uxello in comp.arch.fpga17 years ago 7 replies

Hi all ! I would like to make a Spartan 3 FPGA to reset and reprogram itself from a platform prom after I have reprogrammed the prom using...

Hi all ! I would like to make a Spartan 3 FPGA to reset and reprogram itself from a platform prom after I have reprogrammed the prom using JTAG boundery-scan. Is there any instruction I can send to the FPGA or the prom with JTAG to tell the FPGA to reprogram ? Usually this is done at power-on, but in my case, I can't power-off/on the whole system to make the FPGA to get a new firmwar...


question about xilinx jtag

Started by Anonymous in comp.arch.fpga15 years ago 1 reply

My socket seems not to be in the documentation. It looks a bit like those sockets of harddisk cables expect there are just 2 rows of 8. Is...

My socket seems not to be in the documentation. It looks a bit like those sockets of harddisk cables expect there are just 2 rows of 8. Is this jtag? Where is vdd/gnd/tdi/tdo/tck/tms Which document ?


spartan 3e JTAG programming

Started by katherine in comp.arch.fpga15 years ago 1 reply

Hi guys I have two spartan 3e's and a coolrunner in a single JTAG chain. If I program either FPGA from power up its outputs do not drive,...

Hi guys I have two spartan 3e's and a coolrunner in a single JTAG chain. If I program either FPGA from power up its outputs do not drive, but I can read the JTAG user register and it has the value that I set from "generate programming file" so the binary is in the FPGA but the IO doesn't get driven, presumably the "enable outputs" state in the startup sequence never occurs. When I pro...


XCF02S not seen in the JTAG chain

Started by AugustoEinsfeldt in comp.arch.fpga14 years ago 4 replies

Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now. But like normal days I...

Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now. But like normal days I need to solve this issue asap and thought to ask the list as well. I have a design with a CPLD, a Spartan3 (XC3S400) and a XCF02S memory on the JTAG chain. I cannot see the memory in the JTAG chain, only the CPLD and FPGA. When doing a Get Device ID...


Two JTAG Parallel IV Cable in a single PC.

Started by Pablo in comp.arch.fpga14 years ago 4 replies

Hi everybody, my question is very simple. Has anyone put two JTAG Parallel IV (Parallel) Cable on a PC?. I have connected two FPGA and I...

Hi everybody, my question is very simple. Has anyone put two JTAG Parallel IV (Parallel) Cable on a PC?. I have connected two FPGA and I want to Debug them (in realtime) with two JTAG Cables. First of all I tried to put a USB To Parallel Connector, but Xilinx doesn't accept this Virtual Parallel Port. My second option was putting a PCI Parallel Connector as LPT2. But it fails again. I...