Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)

Started by cpope in comp.arch.fpga15 years ago 8 replies

I'm trying to do something I think should be simple. I've seen several posts about building custom jtag programmers using byte blaster emulators...

I'm trying to do something I think should be simple. I've seen several posts about building custom jtag programmers using byte blaster emulators or xilinx jdrive software, etc. so I hope somebody has already solved this. I have 4 user I/O pins on my V4FX12 device attached to my JTAG scan chain. I want to drive these lines to reprogram the XCF32P prom which my fpga boots from. I am running L...


JTAG Loader tools won't execute

Started by mludwig in comp.arch.fpga15 years ago 5 replies

I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The system...

I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The system cannot execute the specified program" message in the Windows XP Command Prompt. Am I missing something here? Has anybody been able to run these tools and program the instruction ROM via JTAG? Thanks,


Re: Xilinx programmer, many unknown devices...

Started by Matthew Hicks in comp.arch.fpga15 years ago

What board do you have? You might have the wrong kind of cable end for the type of jtag connector on your board. Your board probably has a...

What board do you have? You might have the wrong kind of cable end for the type of jtag connector on your board. Your board probably has a Parallel-(# here) Jtag connector which isn't directly compatible with the single in-line programmer cable end. ---Matthew Hicks > First I need to know where in this header are the jtag pins. Any > ideas. Then we need to make sure the notch is


Programming flash connected to CPLD via JTAG

Started by woko in comp.arch.fpga18 years ago 6 replies

Hello! I want to revitalise a question at was asked in 2001, because I hope something changed during the time. How can a AT49LV001 flash by...

Hello! I want to revitalise a question at was asked in 2001, because I hope something changed during the time. How can a AT49LV001 flash by programmed through a XC9536XL CPLD and its JTAG-connector with really low cost? All address, data and control pins are connected to the CPLD, so ISP via JTAG should be possible.I'm sure there are lots of tools available at this time for programmin...


Altera nios-debug via JTAG

Started by evan in comp.arch.fpga17 years ago

Hi, I have been trying to debugg a simple "hello world" program running in an Altera Cyclone device with Nios 32 (including OCI-Core) via...

Hi, I have been trying to debugg a simple "hello world" program running in an Altera Cyclone device with Nios 32 (including OCI-Core) via JTAG. I can use serial comms for the upload but I need the serial communications available during execution. The problem is that the JTAG upload gives me the following error: # 2005.08.29 13:34:24 (*) nios-init-mdi -i WARNING: Do not attempt to ...


Re: implement the JTAG MASTER --ACT8990 by using FPGA

Started by Antti Lukats in comp.arch.fpga17 years ago 8 replies

"strayblue" schrieb im Newsbeitrag news:Y5-dncZSwMbpxMTfRVn_vg@giganews.com... > I want to implement the JTAG MASTER --ACT8990 by using...

"strayblue" schrieb im Newsbeitrag news:Y5-dncZSwMbpxMTfRVn_vg@giganews.com... > I want to implement the JTAG MASTER --ACT8990 by using FPGA,Does who > have do the same thing? Could someone give me a hand please? > heavens sake why do you want todo this ??! the 8990 is a very old biest, why duplicate it? just make your own JTAG master and


JTAG and Altera Cyclone-IV

Started by dtrang in comp.arch.fpga10 years ago

Hi, I would like to ask for some input. When this device is in JTAG reset state, how does it drive the outputs, hi-Z, 1'b0, 1'1b1, or...

Hi, I would like to ask for some input. When this device is in JTAG reset state, how does it drive the outputs, hi-Z, 1'b0, 1'1b1, or unpredictable? Thx, Dtrang --------------------------------------- Posted through http://www.FPGARelated.com


Weird JTAG lockup issue, where is the BUG?

Started by Antti in comp.arch.fpga16 years ago 10 replies

Hi I have several Spartan3 boards that have a very weird issue, namly when configured with one specific VHDL design using Impact with verify...

Hi I have several Spartan3 boards that have a very weird issue, namly when configured with one specific VHDL design using Impact with verify off then after first programming attempt (status fail with CRC check!) the JTAG chain is reported broken before the FPGA and further configuration or even jtag idcode reading is not possible until complete power off the FPGA. When imact option verify ...


JTAG cable @ 2.5 V - where?

Started by Markus Zingg in comp.arch.fpga16 years ago 5 replies

Hi group I'm a newbee, so please bear with me if this does not make sense. I got a AVNet (MEMEC) Virtex 4 based developper kit based on...

Hi group I'm a newbee, so please bear with me if this does not make sense. I got a AVNet (MEMEC) Virtex 4 based developper kit based on the Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as "a 2.5V compatible JTAG chain header". The pinout is identical to what Xilinx seems to use (14 pins etc.). The docs seem to asume that one must use the Xilinx parallel cable IV whi...


JTAG as UART for PowerPC in XMD.

Started by Pablo in comp.arch.fpga15 years ago 4 replies

Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx provides OPB_MDM as uart...

Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx provides OPB_MDM as uart with C_USE_UART PARAMETER, but in my desing I use PowerPC. In powerPC the debug is done by jtag_cntlr and not by opb_mdm so console says that "opb_mdm_0 is not accessible from processor ppc405_0". Has anyone configured JTAG as UART in PowerPC? Rega...


How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?

Started by Ssa in comp.arch.fpga15 years ago 1 reply

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what...

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what about the JTAG-debug unit? It seems to use the Lattice's JTAG-block. Can I just replace this with a generic JTAG TAP-controller, and then use a Xilinx-hosted Mico32 with a Lattice download-cable?


Altera JTAG problem

Started by Górski Adam in comp.arch.fpga12 years ago 2 replies

Hi all, I need help. How to send single instruction/command thru JTAG interface with altera tools. I have to send FACTORY instruction and I...

Hi all, I need help. How to send single instruction/command thru JTAG interface with altera tools. I have to send FACTORY instruction and I know binry code for this instruction but I don't know how to send it. Or in other words I have to reenable jtag interface blocked because of anti tamper feature ( in my design ) Please help. BR Adam


PROTEL DXP 2004 / NANOBOARD / 3rd Part board

Started by Repzak in comp.arch.fpga18 years ago

Hey... i hope there is a clever guy reading this channel and using Protel.... i have buyed a 3rd party FPGA board with a SpartanII...

Hey... i hope there is a clever guy reading this channel and using Protel.... i have buyed a 3rd party FPGA board with a SpartanII SX2S300E... There is onboard Jtag (normal Xillinx Jtag) But when i want to use it with protel and use soft instruments etc... i have to connet "2 Jtags" at one time, one for the Hard Jtag to program the FPGA and one to normal I/O Pins... Quite easy just a m...


JTAG ID code 0xFFFFFFFF

Started by BERT in comp.arch.fpga15 years ago 3 replies

Hi, I need some help with my Altera Dev Kit (STRATIX DSP S80 Development Board Rev 1.2). I no longer seem to be able to program my device....

Hi, I need some help with my Altera Dev Kit (STRATIX DSP S80 Development Board Rev 1.2). I no longer seem to be able to program my device. It was working properly until I started getting the following error: "Error: Can't configure device. Expected JTAG ID code 0x20070DD for device 1, but found JTAG ID code 0xFFFFFFFF." Also, when I use the "Auto Detect" feature of Quartus II Programm...


Program Xilinx with Altera JTAG Programmer?

Started by jackm in comp.arch.fpga7 years ago 13 replies

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship...

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship from China and are fake copies I assume, they cost less than $7 inc shipping. If I download and install Altera Quartus II software can I use that to JTAG program my device file compiled in Xilinx ISE? Thanks for any help.


JTAG: First of 4 Spartan-3E always UNKNOWN

Started by Anonymous in comp.arch.fpga14 years ago 12 replies

Hi All, I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For configuration I have both JTAG and slave serial access. Slave serial...

Hi All, I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For configuration I have both JTAG and slave serial access. Slave serial works fine. However, when I try to identify the JTAG chain the first FPGA always comes back UNKNOWN. If I'm correct, impact's response to the identify command lists the devices in reverse order. So the when it reports this: '1': : Manufacturer's ...


jtag loader for picoblaze

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

hi all we have implemented a picoblaze in vertex 4 kit and we r in the path of implementing JTAG loader to reconfigure block rom ,which is...

hi all we have implemented a picoblaze in vertex 4 kit and we r in the path of implementing JTAG loader to reconfigure block rom ,which is used to change the program ROM. any one have an idea on implementing JTAg loader in VERTEX 4. we tried but it is giving a error of " virtex 2 boundary scan failed to match for virtex 4"" please help us to overcome this problem thanks umesha ...


Trouble using ChipsCope Pro with MicroBlaze

Started by arkaitz in comp.arch.fpga18 years ago 7 replies

Hi all, Has anybody tried Chipscope Pro with a MicroBlaze based system? I am using JTAG-Uart for debugging purposes and now I want to...

Hi all, Has anybody tried Chipscope Pro with a MicroBlaze based system? I am using JTAG-Uart for debugging purposes and now I want to use ChipScope Pro at the same time, but when I try to implement it generates an error with BSCAN. I know that JTAG-Uart uses a BSCAN and ChipScope also needs another one. If I take out the JTAG-Uart from the design it works. So is there any possible s...


Strange JTAG TCK problems with Spartan XC3S400

Started by Ulrich Bangert in comp.arch.fpga16 years ago 1 reply

Addressed to the XILINX insiders: I have made me myself a small pcb which is basically a replica of the simple Xilinx JTAG download cable....

Addressed to the XILINX insiders: I have made me myself a small pcb which is basically a replica of the simple Xilinx JTAG download cable. This JTAG interface works well with Xilinx CPLDs and also with Altera FPGAs and CPLDs (after some pin mapping on the printer port side, of course, making it look like a Byteblaster cable to the Altera tools). However, if I try to program a Spartan XC3...


accesing JTAG ports on GPIOs

Started by maverick in comp.arch.fpga15 years ago 10 replies

Hi there, I have a virtex II board (xc2v1000), unfortunately no jtag signals are routed on this board (TMS, TDI, TDO, TCK ). This really...

Hi there, I have a virtex II board (xc2v1000), unfortunately no jtag signals are routed on this board (TMS, TDI, TDO, TCK ). This really deprives me from using ChipScope pro on this board to debug my design. Is it possible somehow to tap the jtag ports internally and route them to GPIOs which are available on th board! In that case, I will insert the ChipScope Pro core in my design in the no...