Reading back SRAM content via JTAG?

Started by moe in comp.arch.fpga19 years ago 3 replies

I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge. Q: Can I use JTAG interface to...

I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge. Q: Can I use JTAG interface to verify what I wrote into the SRAM, instead of the traditional read-back method? My setup and the reason for wanting to do it this way is : An FPGA interfaces to a sync SRAM (QDR with separate write/read port). The FPGA can write to the SRAM using ...


2 FPGAs /w programming FLASH in one JTAG chain

Started by Toni Merwec in comp.arch.fpga15 years ago 6 replies

Hi there, currently I am designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. It should be possible to program them with onboard...

Hi there, currently I am designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. It should be possible to program them with onboard Xilinx Platform FLASH PROMs as well as via JTAG with the IMPACT software. For ease of use and debugging all components should be part of one coherent JTAG chain. Now I'd like to know HOW to connect two FPGAs and two Platform FLASH devices in one JT...


PowerPC and JTAG

Started by BrakePiston in comp.arch.fpga18 years ago 5 replies

Hi everybody, just a quick question. Can the PowerPC in a Virtex II Pro, be routed to control the JTAG hardware? By that I mean provide...

Hi everybody, just a quick question. Can the PowerPC in a Virtex II Pro, be routed to control the JTAG hardware? By that I mean provide instruction and data to the TAP Thanks!!


JTAG pins of the xc2s200E for user I/O

Started by Adriano in comp.arch.fpga16 years ago 7 replies

I'm implementing some Image Processing algorithms in VHDL, I'm testing these algorithms on the FPGA Spartan IIE xc2s200E. Is there any way to...

I'm implementing some Image Processing algorithms in VHDL, I'm testing these algorithms on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins of the xc2s200E for user I/O? I want to download data from the PC, via a Parallel Port to JTAG Port on the xc2s200E.


JTAG Registers

Started by Prashanth in comp.arch.fpga18 years ago 3 replies

Hi Folks, Is it possible to send user commands through JTAG to the internal Logic in the FPGA ? More Specifically a Spartan 3...

Hi Folks, Is it possible to send user commands through JTAG to the internal Logic in the FPGA ? More Specifically a Spartan 3 FPGA. Thanks, Prashanth


JTAG USB interface

Started by dajjou in comp.arch.fpga14 years ago 3 replies

Hello everybody, I have no idea how to start !! in fact i want to use USB JTAG interface in order to communicate with my FPGA ( Virtex 4),...

Hello everybody, I have no idea how to start !! in fact i want to use USB JTAG interface in order to communicate with my FPGA ( Virtex 4), I mean using the FTD2232C instead of XILINX USB programmer. please i need your help .


system ace - ERROR: IMPACT:477 - what is this?

Started by sutejok in comp.arch.fpga16 years ago 1 reply

impact:477 the bsdl for device 'UNKNOWN' is out of date does anyone have any idea? I have this error when working with system ace. i'm trying...

impact:477 the bsdl for device 'UNKNOWN' is out of date does anyone have any idea? I have this error when working with system ace. i'm trying to make my Virtex4 XtremeDSP kit to be self-programmabel using system ace. I built the system ace circuit and encountered this error. What i did was i hooked up the jtag cable to my board's 'test jtag' port, and i hooked up my 'config jtag' port to t...


debuging power_pc + microblaze

Started by Anonymous in comp.arch.fpga16 years ago

Hi all, Can I create an EDK based system containing both a PPC and MB while connecting debug peripheral to both of them at the same time...

Hi all, Can I create an EDK based system containing both a PPC and MB while connecting debug peripheral to both of them at the same time (via jtag-> xmd-> gdb) ? (mdm for MB and jtag debug port for PPC). Thanks, Mordehay.


Free JTAG board test software?

Started by Richard Tierney in comp.arch.fpga17 years ago

Not specifically an FPGA question, but does anyone know of any free JTAG testing software? I've got (or will have) lots of assembled boards to...

Not specifically an FPGA question, but does anyone know of any free JTAG testing software? I've got (or will have) lots of assembled boards to test, and I'm thinking about using JTAG. The problem is, the software needs to work out for itself what the netlist is from a known good board. I can buy software to do this, but it'll double the cost of the assembled board. Cheers RT


JTAG Configuration

Started by Ivan in comp.arch.fpga18 years ago 4 replies

Hi, Did anyone know what is the Xilinx recommended pull-up register value for the JTAG configuration pins (TCK, TMS, TDI, TDO and M0-M2)...

Hi, Did anyone know what is the Xilinx recommended pull-up register value for the JTAG configuration pins (TCK, TMS, TDI, TDO and M0-M2) for Virtex4? Thanks, Ivan


Is there any way to disable JTAG for Sptantan3AN

Started by Goli in comp.arch.fpga14 years ago 10 replies

Hi, We want to make Spartan3AN as One Time Programmable. We want to program it once and then disable JTAG. Is it possible to do that? How can...

Hi, We want to make Spartan3AN as One Time Programmable. We want to program it once and then disable JTAG. Is it possible to do that? How can we do that? -- Goli


Debugging software in an ACEX device with Nios 32 via JTAG

Started by Joe Sabater in comp.arch.fpga19 years ago 2 replies

Hi, I have been debugging a software application running in an Altera APEX device with Nios 32 (including OCI-Core) via JTAG with no problem...

Hi, I have been debugging a software application running in an Altera APEX device with Nios 32 (including OCI-Core) via JTAG with no problem at all. Now, I am trying to do the same with an ACEX (EP1K100FC256-2) with no success. The problem seems to be when the debugger tries to connect to the remote target via JTAG. After issuing a "nios-debug" command under SOPC Builder shell I get the fo...


PROG_B and JTAG

Started by Marco in comp.arch.fpga16 years ago 1 reply

Hi, I'll not use PROG_B with my Spartan3, should I just pull-it up with 10k? Is it true that I can alway access the FPGA through the JTAG port...

Hi, I'll not use PROG_B with my Spartan3, should I just pull-it up with 10k? Is it true that I can alway access the FPGA through the JTAG port even if the M0-M2 are hardware-set for slave/master serial? Thanks, Marco


JTAG programming of Altera Cyclone and CONF_DONE

Started by Nevo in comp.arch.fpga16 years ago 10 replies

All, I'm having an extraoridnarily difficult time with my first FPGA project and am very frustrated. I have a board designed around the...

All, I'm having an extraoridnarily difficult time with my first FPGA project and am very frustrated. I have a board designed around the EP1C6 Cyclone device. The Quartus programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able to initiate programming the device over the JTAG port, but Quartus gives me an error CONF_DONE failed to go high on device 1. I reviewed the...


How do I erase an Altera EPM7064 with JTAG lockout

Started by John Kortink in comp.arch.fpga16 years ago 1 reply

Subject says it all really. I'd like to erase a number of EMP7064SLC44's that have been programmed with JTAG disabled. Anyone have...

Subject says it all really. I'd like to erase a number of EMP7064SLC44's that have been programmed with JTAG disabled. Anyone have the 'secret formula' or the special programmer equipment that can do it ?


FLASH memory programming with Altera NIOS and same question for Xilinx

Started by George in comp.arch.fpga18 years ago 5 replies

I'm designing an Altera NIOS (could be Xilinx equivalent) CPU system with external FLASH (and RAM) memory. The Altera FPGA (probably ACEX1K)...

I'm designing an Altera NIOS (could be Xilinx equivalent) CPU system with external FLASH (and RAM) memory. The Altera FPGA (probably ACEX1K) has a JTAG port so when I get the 1st prototype I can download a configuration using the JTAG. But how can I program the FLASH when it's soldered on the board? I can't find a FLASH with a JTAG interface. I can't preprogram the FLASH since I don't h...


JTAG programmers

Started by Rob Judd in comp.arch.fpga19 years ago 4 replies

Hi y'all, Right, we're making some progress on parts sourcing, thanks in no small way to some of you out there who shall remain nameless to...

Hi y'all, Right, we're making some progress on parts sourcing, thanks in no small way to some of you out there who shall remain nameless to avoid embarrassment. (Thanks!) What has come up next is the requirement for a JTAG programmer. I've found one here: http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm but wonder whether using it on devices only capable of 3v3 or lower may ki...


JTAG vs. Passive Serial Config speed

Started by Kolja Waschk in comp.arch.fpga18 years ago 1 reply

Hi Is there a significant difference in the time it takes to download a configuration to an Altera Cyclone (EP1C6) using JTAG, vs. the...

Hi Is there a significant difference in the time it takes to download a configuration to an Altera Cyclone (EP1C6) using JTAG, vs. the Passive Serial Configuration method? In January, Greg Steinke here mentioned a program to program a Serial Configuration Device (e.g. EPCS1) _through_ a Cyclone, with the programmer attached only to the Cyclone's JTAG port. It was beta, then. Is this opt...


Actel APA1000 and JTAG

Started by Niv in comp.arch.fpga15 years ago 2 replies

Hi all, We are trying to programme a FLASH memory linked to a APA1000. However, we have a data-blaster that should programme the FLASH quickly,...

Hi all, We are trying to programme a FLASH memory linked to a APA1000. However, we have a data-blaster that should programme the FLASH quickly, providing we can drive the write signal from teh APA to a high imedance state via the JTAG port. It seems we're having trouble doing this. Is it possible to force/ drive a particular pin to 'Z' via JTAG? The data-blaster write is driven through...


Can I capture the jtag TDO pin of a Spartan3AN

Started by fpgauser in comp.arch.fpga13 years ago 3 replies

Hi, The cell BSCAN_SPARTAN3A allows to monitor the jtag input pins TCK, TDI and TMS of a Spartan3A chip. I was curious, whether I would...

Hi, The cell BSCAN_SPARTAN3A allows to monitor the jtag input pins TCK, TDI and TMS of a Spartan3A chip. I was curious, whether I would also be able to capture the value of the TDO pin (without soldering or wiring it back to another pin of the 3AN) If yes, what would be the trick? Thanks in advance and bye