JTAG, Master Serial Mode

Started by Chao in comp.arch.fpga18 years ago 2 replies

Hello, I have one general question concerning the FPGA supported configuration mode. I am using Xilinx ISE iMpact to program Spartan-3. I...

Hello, I have one general question concerning the FPGA supported configuration mode. I am using Xilinx ISE iMpact to program Spartan-3. I use the JTAG Cable-IV to download the bitstream to the Spartan-3. Meanwhile I set up the configuration jumper on board to JTAG mode (i.e. M0,M1,M2=0,1,0). That works fine. But if I set up the jumper to MASTER-SERIAL (i.e. M0,M1,M2=1,1,1) mode, I can sti...


RISCWatch and JTAG

Started by Krzysztof Szczepanski in comp.arch.fpga17 years ago 1 reply

Hello! Is there any hardware documentation to RISCWatch of PPC405 in Xilinx devices? I look for waveforms describe the signals of the...

Hello! Is there any hardware documentation to RISCWatch of PPC405 in Xilinx devices? I look for waveforms describe the signals of the interface. Is there any JTAG vendor specific commands used to debug the processor? Thanks!!! krzysiek


PPC and Chipscope?

Started by Anonymous in comp.arch.fpga16 years ago 8 replies

I am starting a new design using V4FX parts. I have only one JTAG connection so far. Is it possible to simultaneously run the debugger and a...

I am starting a new design using V4FX parts. I have only one JTAG connection so far. Is it possible to simultaneously run the debugger and a chipscope session so I can debug problems between the micro and the fpga fabric? If not, do I need a second JTAG and how do I wire it? Thanks, Clark


use of JTAG pins

Started by teo_80 in comp.arch.fpga17 years ago 1 reply

Can I use JTAG pins as a user I/O on an Altera Stratix Device ? Matteo

Can I use JTAG pins as a user I/O on an Altera Stratix Device ? Matteo


JTAG USB Circuit

Started by fecs2 in comp.arch.fpga17 years ago 5 replies

anyboydy knows how to find the circuit or schematic fo make an JTAG USB cable?

anyboydy knows how to find the circuit or schematic fo make an JTAG USB cable?


JTAG in-system programming of PROM devices

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hi, I've a question regarding in-system programming of prom devices using the JTAG (ieee 1532) protocol. I implemented a programming...

Hi, I've a question regarding in-system programming of prom devices using the JTAG (ieee 1532) protocol. I implemented a programming algorithm based on the JTAG TAP controller state diagram (i.e. shown in xilinx app. note XAPP503). The implemented command sequences (i.e. for erase, program, read-prom, etc.) are taken from SVF files generated by the XILINX Impact tool and the corresponding BS...


FPGA to ASIC + JTAG chain insertion

Started by Laurent Gauch in comp.arch.fpga17 years ago

Hi all, We have to do a FPGA-to-ASIC conversion with JTAG chain insertion. The design was tested on spartan-II and was converted to ATMEL...

Hi all, We have to do a FPGA-to-ASIC conversion with JTAG chain insertion. The design was tested on spartan-II and was converted to ATMEL MG2 successfully via Leonardo Spectrum (functional test and sdf timing). Now we have to use MENTOR DFT Suite for the JTAG insertion and test coverage. The documentation from MENTOR is very complet, and/or maybe a bit too complet. My question...


Re: longest webcase record -- understandably so

Started by rickman in comp.arch.fpga16 years ago

Austin Lesea wrote: > Colin, > > So, the device should take on the new configuration for the IO standard > once configured. Yes? > > ...

Austin Lesea wrote: > Colin, > > So, the device should take on the new configuration for the IO standard > once configured. Yes? > > JTAG or normal IO use should not make any difference: the IO pin can > not revert to the default programming just because JTAG is in use? > > Is this what you have confirmed? Yes, or No, please. I already know my > mind doesn't work the same as yours.


Xilinx XC9500 Jtag instructions?

Started by linnix in comp.arch.fpga16 years ago 4 replies

Does anyone know where to find the XC9500 Jtag programming instructions? I have one for the XCR3000 (cool runner) and looking for the...

Does anyone know where to find the XC9500 Jtag programming instructions? I have one for the XCR3000 (cool runner) and looking for the equivalence for XC9500 The XCR3000 jtag spec has detail info down to the TMS/TDI/TDO level. I am sure there is one for XC9500 somewhere. I can't even find the XCR3000 on xilinx's web anymore.


Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software

Started by Scott Gravenhorst in comp.arch.fpga14 years ago 8 replies

I have a Spartan-3A DSP 1800A development board which comes with no cable. I understand that Xilinx makes a cable for $150 that works with...

I have a Spartan-3A DSP 1800A development board which comes with no cable. I understand that Xilinx makes a cable for $150 that works with iMPACT. There is also a 6 pin JTAG conntector on the board. I already know that the Digilent JTAG-USB cable will NOT work with either iMPACT nor Adept. Communication with Digilent indicates that they may support this FPGA in the future, but it is cu...


FPGA : Chip-scope + spartan-3e

Started by bijoy in comp.arch.fpga16 years ago

Hi I have a board with Spartan-3e with SPI-interface. i am using the JTAG interface to program the SPI-flash. all JTAG connections are...

Hi I have a board with Spartan-3e with SPI-interface. i am using the JTAG interface to program the SPI-flash. all JTAG connections are correct. when i connect chip-scope it is not detecting any device in the JTAG chain. tried using iMPACT tool also, there also i am not able to detect the FPGA in the chain. am using Parallel cable III. and the cable is OK as we are using the same cable ...


XCS10-84PC: How JTAG-Pins as I/O ?

Started by (beta-) Frank Nitzsche in comp.arch.fpga18 years ago 2 replies

Hello all, I use Xilinx Foundation 1.5 and VHDL for a SPARTAN XCS-10 . I have to use the JTAG-Pins as I/O-pins (TDI, TCK, TMS = I/O, TDO=O)....

Hello all, I use Xilinx Foundation 1.5 and VHDL for a SPARTAN XCS-10 . I have to use the JTAG-Pins as I/O-pins (TDI, TCK, TMS = I/O, TDO=O). How to do? The data-sheet give me not enough information... Thanks Frank smartie@snafu.de


Configuring FPGA & PROM with serial Cable (DB9)

Started by Y Nagaonkar in comp.arch.fpga18 years ago 1 reply

I am trying to program my FPGA board without a Xilinx Parallel Cable. I would like to able to program the FPGA using the Serial Cable...

I am trying to program my FPGA board without a Xilinx Parallel Cable. I would like to able to program the FPGA using the Serial Cable and Serial Port (DB9). Also I am not sure if I understand JTAG correctly, but is there a way to implement the JTAG interface on serial cable, the way the Xilinx XChecker Cable does. Isnt JTAG simply a translationof voltage logic levels. I was not able ...


how to write data to a register in the FPGA

Started by haowen in comp.arch.fpga13 years ago 1 reply

I want to write data to a register in the FPGA via jtag. I use the BSCAN_VIRTEX4 and write a tcl to write the data. But it did not work. This is...

I want to write data to a register in the FPGA via jtag. I use the BSCAN_VIRTEX4 and write a tcl to write the data. But it did not work. This is the first time that I use the tcl and jtag. I don't know why? The promblem is the tcl part or the verilog part? The following is my code, I want to write data to the "mux_reg". module jtag( output wire o_tdo); reg[2:0] ...


JTAG FPGA Debugging

Started by Silver in comp.arch.fpga15 years ago 5 replies

Hi everyone! I'm new to the group and quite a beginner in FPGA business. I have this very general question on BSDL files and JTAG - is there...

Hi everyone! I'm new to the group and quite a beginner in FPGA business. I have this very general question on BSDL files and JTAG - is there any possibility to include any internal signal (not connected directly to the output pin) in the scan register? Chris


USB JTAG

Started by John Evans in comp.arch.fpga14 years ago 3 replies

Hello All, Does anyone know if there is a cheaper alternative to the Xilinx USB JTAG programmer. ? The price of $300 from avnet is rather...

Hello All, Does anyone know if there is a cheaper alternative to the Xilinx USB JTAG programmer. ? The price of $300 from avnet is rather expensive in my opinion (and for my budget..). I've been using xilinx cable IV, but it's not really working as reliable or fast as one could wish for. Another problem is that my laptop doesn't have a parallel port which is very annoying. Than...


Downloading some data from flash memory thru JTAG.

Started by Anonymous in comp.arch.fpga14 years ago

Hi. I have common configuration scheme for Altera Stratix II: flash memory + Max device + Stratix II. Flash memory configured by FPP method...

Hi. I have common configuration scheme for Altera Stratix II: flash memory + Max device + Stratix II. Flash memory configured by FPP method thru JTAG. Is there any simple method to download flash memory contents thru Stratix II device and thru JTAG port to computer?


Debug multiple FPGAs using ChipScope via single JTAG chain

Started by Speed in comp.arch.fpga12 years ago 4 replies

Dear All, We are planning to design a board with four FPGAs to emulate X86 CPU. The FPGA=92s JTAG ports are serially chained together. My...

Dear All, We are planning to design a board with four FPGAs to emulate X86 CPU. The FPGA=92s JTAG ports are serially chained together. My problem is that whether the Xilinx=92s ChipScope can support debugging multiple FPGAs via a single JTAG chain at the same time? So we can set different trigger conditions to different FPGA chips at the same time and watch the sampled data from ChipScope....


RAM programming by JTAG (i need some serious help)

Started by Michel Bieleveld in comp.arch.fpga18 years ago 3 replies

I am trying to achieve something that probably thousand have done before me. I want to program a sram module that is attached to my...

I am trying to achieve something that probably thousand have done before me. I want to program a sram module that is attached to my fpga (xc2s300). I have a parallal cable programmer that is compatible with imPact. Now i am wondering what do you use (software/hardware) to program ram by jtag. There must be an easy way !? Michel Bieleveld.


Memory or registers and JTAG

Started by AL in comp.arch.fpga17 years ago 3 replies

Hi, I read a lot of stuffs on JTAG and SVF file, but I still can't figure out how to read back multiple memory spaces or multiple registers via...

Hi, I read a lot of stuffs on JTAG and SVF file, but I still can't figure out how to read back multiple memory spaces or multiple registers via JTAG. I used BSCAN_SPARTAN3 and USER1 Register, but that only allows you to read back one register. I need to read back at least 10 registers or memory spaces via JTAG. Is it possible to do this at all? Thanks, AL