Kintex UltraScale board with two DDR4 interfaces?

Started by Owenh in comp.arch.fpga3 years ago

Hello, I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be possible to run two separated DDR4 controllers (i.e., a board...

Hello, I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be possible to run two separated DDR4 controllers (i.e., a board where there is more than one address bus for the DDR4 chips). In case someone knows about such a board, I would be happy to know. Thank you :-) --------------------------------------- Posted through http://www.FPGARelated.com ...


Interface Xilinx KC705 to BeagleBone?

Started by pfraser in comp.arch.fpga5 years ago 16 replies

I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx KC705 Kintex development board. This will...

I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx KC705 Kintex development board. This will give me much more CPU processing power than a microblaze could. I thought I could probably do it with a passive interface because the Kintex can deal with 3.3 Volt I/O. I'd probably use a Xilinx 105 debug board on the FMC HPC connector, and hand bu...


Speed of GTX transceivers in Kintex 7 in FBG package?

Started by Anonymous in comp.arch.fpga2 years ago

Hi, I have seen contradictory data about speed of GTX transceivers in Kintex 7 in FBG packages: 1. The datasheet (...

Hi, I have seen contradictory data about speed of GTX transceivers in Kintex 7 in FBG packages: 1. The datasheet ( http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf , page 54 ) states that the maximum speed is 6.6 Gb/s 2. The answer record http://www.xilinx.com/support/answers/50299.html states explicitly: " Limit the maximum line rate to 6.6 Gb


Terminating an Aurora link in a PC

Started by Anonymous in comp.arch.fpga10 months ago 4 replies

Hi I have two devices communicating via an Aurora link (single lane, full duplex) over SFP + optical cables. I need to replace one of them with...

Hi I have two devices communicating via an Aurora link (single lane, full duplex) over SFP + optical cables. I need to replace one of them with a PC (testing, emulation etc etc) I see several (HITEC for example) offering PCIe cards featuring Kintex FPGA that look like they would do the job but I don't have a resource to do any HDL work. Can anyone recommend an off the shelf card?


Data transfers between MicroBlaze and VHDL

Started by Robert Higginbotham in comp.arch.fpga5 years ago 11 replies

I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am trying to figure out a way...

I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am trying to figure out a way that I could output the data from the MicroBlaze to a VHDL module and also the reverse transfer. This way I can capture the data, use it in some calculations, and then also pass it back to the MicroBlaze for further use. I am new to Embedded Desi...


Xilinx BULLSHITIX-8, when?

Started by Antti in comp.arch.fpga7 years ago 22 replies

the X-7 roadmap and all device table are no online, and the ARM11 is coming is also all public knowledge, but.. where? in what...

the X-7 roadmap and all device table are no online, and the ARM11 is coming is also all public knowledge, but.. where? in what family? spartan is dead, now is Artix, und Kintex? but where is ARM11? in BULLSHITIX-8 release? I wonder. of course its very interesting to see how much mess Xilinx is able to organize with the 7 series, right now Xilinx online shop list exactly 2 devices of ...


Partial reconfiguration: bus macros

Started by chthon in comp.arch.fpga6 years ago

Hello, I am trying to do DPR on an Atlys board, which uses Spartan-6. It seems I c= an only solve my problem if I revert to bus macros...

Hello, I am trying to do DPR on an Atlys board, which uses Spartan-6. It seems I c= an only solve my problem if I revert to bus macros (Partitions are only sup= ported for Virtex/Kintex and you need an additional license, differential P= R is usable if you do not use block RAMs on the Spartan-6). However, the latest references I can find on bus macros date from 2007, and= searching on X...


ise 32b or 64b?

Started by mmihai in comp.arch.fpga5 years ago 2 replies

Hi! Using Xilinx flow (command line, ISE 13.4)... 32b version vs 64b (under Linux, 64b OS)... memory usage: || | 32b | 64b | ...

Hi! Using Xilinx flow (command line, ISE 13.4)... 32b version vs 64b (under Linux, 64b OS)... memory usage: || | 32b | 64b | | xst | 1614M | 2986M | | map | 1563M | 2889M | | par | 1365M | 2404M | Also the 32b runtime is faster than 64b.... The above table is from a Kintex-7 target running on a i5 machine, 8G RAM. Similar numbers are seen for a ...


bitstream support for Artix 7 in torc?

Started by Anonymous in comp.arch.fpga3 years ago

Does TORC provide bit stream generation for Artix 7 devices??? Looking at the torc source files, i see classes only for bistrem for Spartan and...

Does TORC provide bit stream generation for Artix 7 devices??? Looking at the torc source files, i see classes only for bistrem for Spartan and Virtex family. Can it be used for Artix device?? If not, will there be support for bitstream generation for any 7 series fpga from Artix and Kintex family???


Sending and receiving of 10GBASE-R Ethernet frames via GTX transceivers in FPGA?

Started by Anonymous in comp.arch.fpga4 years ago 2 replies

Hi, I'm working on a code which is supposed to send and receive 10GBASE-R Ethernet frames via SFP+ modules connected to the GTX transceiver in...

Hi, I'm working on a code which is supposed to send and receive 10GBASE-R Ethernet frames via SFP+ modules connected to the GTX transceiver in a Kintex-7 FPGA. I've read the section 4 of 802.3-2012 standard and the ug476_7Series_Transceivers.pdf, but it still unclear to me how to send the correct Ethernet frame, directly driving the TX Gearbox of the GTX... As the core is supposed to be u...