LVDS pin assignment

Started by in comp.arch.fpga12 years ago 4 replies

Hi, I am designing the following converter: LVDS -> some processing -> LVDS. Each LVDS Interface has 3 channels and 1 clock channel at...

Hi, I am designing the following converter: LVDS -> some processing -> LVDS. Each LVDS Interface has 3 channels and 1 clock channel at about 300 MHz (differential clock rate). My question is if I should use GLCK pins for the incoming LVDS clock? Should I also use GLCK pins for the outgoing LVDS clock? I don't think so, because there is no OBUFGDS. Or does it make sense to use GCLK p


LVDS Receiver in FPGA

Started by woko in comp.arch.fpga9 years ago 4 replies

Hi FPGA specialist, we are would like to know if it is currently possible to implement high speed LVDS receiver or transmitter in...

Hi FPGA specialist, we are would like to know if it is currently possible to implement high speed LVDS receiver or transmitter in FPGAs. Our next gerneration PCB board would have about 12 LVDS receiver (SN65LV1224B) , 6 LVDS transmitter (SN65LV1023A) and an FPGA onboard. Please note that the LV1224 and LV1023 transmit thair LVDS in a single differential line, there is no LVDS clock pai...


Re: LVDS output pins of Altera Cyclone II

Started by only...@online.ms in comp.arch.fpga11 years ago 1 reply

I'm trying to use a FPGA to control a flat panel display that has LVDS inputs. Displays try to draw current from active LVDS lines if the power...

I'm trying to use a FPGA to control a flat panel display that has LVDS inputs. Displays try to draw current from active LVDS lines if the power supply of the panel is switched off. That is very harmful for the TFT and sooner or later it gets destroyed. That is why I have to tri-state the LVDS outputs. Every LVDS driver IC on the market has an "output enable" signal. So why shouldn't th...


Using LVDS in Lattice ECP3

Started by PGS in comp.arch.fpga8 years ago 3 replies

We need a quick guide about how to instantiate a LVDS input and a LVDS output on the ECP3. Using the VHDL language (and Symplicity), we would...

We need a quick guide about how to instantiate a LVDS input and a LVDS output on the ECP3. Using the VHDL language (and Symplicity), we would like to use a set of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). I would expect, that I could instantiate a LVDS-input-cell by naming two input ports and providing their proper "LOC" attribute (say again for AN and AP), and the...


Lattice / M-LVDS

Started by Metin in comp.arch.fpga10 years ago 1 reply

Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LVDS? Are they true...

Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LVDS? Are they true M-LVDS driver/receivers? What are the deviations from the TIA/EIA-899 specification? Finally are They current-mode drivers? Thanks.


help with Xilinx LVDS syntax

Started by Morgan in comp.arch.fpga11 years ago 1 reply

I apologize if this questions has been answered already. I was unable to find an answer in my search through this group. If you have any...

I apologize if this questions has been answered already. I was unable to find an answer in my search through this group. If you have any experience using LVDS with Xilinx FPGAs, please help. Q: If I have a LVDS input, must my top-level entity specify both the N and P ports, or is there a way to specify that a port should use LVDS in a constraint file and have the Xilinx tools infer the c...


regarding changing serial data out to LVDS form

Started by ekav...@gmail.com in comp.arch.fpga11 years ago 4 replies

hi all, i have serial data out in my design and i need to convert it to LVDS signal how can i covert it to LVDS . my end system needs...

hi all, i have serial data out in my design and i need to convert it to LVDS signal how can i covert it to LVDS . my end system needs differential data as input so i need to convert to LVDS. i have written code in vhdl and data out is ready which is serial data . i am using spartan 3e fpga..... can any one please explain how to change to LVDS. regards srikanth


LVDS via Emulation

Started by Netoko Young in comp.arch.fpga10 years ago 1 reply

Hi all, I've just read something about LVDS via emulation, in the datasheet of the FPGA its specified that some banks natively support LVDS...

Hi all, I've just read something about LVDS via emulation, in the datasheet of the FPGA its specified that some banks natively support LVDS while some other banks are specified to support LVDS in emulation only, does this mean that to support LVDS an external resistor is needed? Thanks, Neto


Re: LVDS output pins of Altera Cyclone II

Started by only...@online.ms in comp.arch.fpga11 years ago

> tentacle (onlyspam@online.ms) wrote: > > > I'm trying to use a FPGA to control a flat panel display that has LVDS > > inputs. Displays try...

> tentacle (onlyspam@online.ms) wrote: > > > I'm trying to use a FPGA to control a flat panel display that has LVDS > > inputs. Displays try to draw current from active LVDS lines if the power > > supply of the panel is switched off. > > > > That is very harmful for the TFT and sooner or later it gets destroyed. > > > > That is why I have to tri-state the LVDS outputs. > > Didn't know that >


LVDS on Spartan 3

Started by Chris Cheung in comp.arch.fpga13 years ago

hi all, I am new to the LVDS stuff. I am going to implement a LVDS transceiver on XC3S400. I got the XAPP622 application note (talk...

hi all, I am new to the LVDS stuff. I am going to implement a LVDS transceiver on XC3S400. I got the XAPP622 application note (talk about using LVDS on VirtexII and VirtexII pro) from Xilinx sites. I am wondering if the same idea could apply to Spartan 3 (I know Spartan 3 runs slow than Virtex)? Is there any SER-DES core avaliable now for Spartan 3 (I know there is none now on ISE....


Virtex II LVDS plus DDR?

Started by Mark in comp.arch.fpga13 years ago 1 reply

Howdy Gurus, I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear...

Howdy Gurus, I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear explanation yet of the two being used together. DDR by itself is pretty obvious, but the LVDS appears to work by a magical connection between two neighboring IOBs. For an LVDS input pair (Dp and Dn) coming in at DDR, does the differential-to-single-ended ...


LVDS in Cyclone-II

Started by John_H in comp.arch.fpga11 years ago 13 replies

Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't...

Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't true differential drives: an external resistor network is needed to produce proper LVDS levels like in the "old days." Does anyone here have experience with the LVDS drivers? I imagine I'll end up with 0603 resistors rather than a Bourns network...


Problems with 7:1 LVDS Tx using OSEDES (Xilinx)

Started by rao in comp.arch.fpga11 years ago 3 replies

Hi, I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA) and trying to use the approach as specified in xilinx app note...

Hi, I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA) and trying to use the approach as specified in xilinx app note XAPP704 (virtex-4 high speed single data rate LVDS transceiver). The reference design that xilinx provided is for 4:1 (4 parallel data goes to 1 channel of LVDS) and it works fine but when I try to change the parameters to operate as 7:1 the de...


max lvds IO speed on V2Pro

Started by sjulhes in comp.arch.fpga11 years ago 1 reply

Hi, We have to interface a V2Pro with a DSP's communication ports which have LVDS links up to 500Mhz ( taken from datasheet ). We have some...

Hi, We have to interface a V2Pro with a DSP's communication ports which have LVDS links up to 500Mhz ( taken from datasheet ). We have some experience on V2Pro LVDS I/O but at slow speed and we are wondering what speed we will be able to reach with this LVDS DSP link. DSP and FPGA are on the same board at a reasonnable distance ( something like 10-15 cm ). Does someone has a feedbac...


LVDS inputs on Cyclone II

Started by nospam in comp.arch.fpga11 years ago 14 replies

Some time ago I did some experimentation (for a very cost sensitive application) with a Spartan 3 part using an LVDS differential input as...

Some time ago I did some experimentation (for a very cost sensitive application) with a Spartan 3 part using an LVDS differential input as a voltage comparator for a crude delta sigma ADC. The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the 3.3v supply and the differential input voltage was (obviously) limited to whatever it took drive the LVDS input one way or the...


LVDS problem/chipscope VIRTEX4

Started by Yttrium in comp.arch.fpga12 years ago

Hey, I just got a board with a virtex4 and there is a LVDS connection on it and another LVDS input bank where the clock oscillators are...

Hey, I just got a board with a virtex4 and there is a LVDS connection on it and another LVDS input bank where the clock oscillators are connected to. that bank is a Vcco=3.3V bank but has a 2.5V LVDS connection, but since http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&ge tPagePath=16830 says this is not a problem i hope this is not the problem. Now the proble...


DVI - LVDS controller

Started by helix in comp.arch.fpga11 years ago 3 replies

Hello all, I am thinking of building a device which will convert DVI output from my graphics card to LVDS to drive my LCD panel. I was...

Hello all, I am thinking of building a device which will convert DVI output from my graphics card to LVDS to drive my LCD panel. I was originally thinking of using ICs but I wondered if it was possible to do using an fpga? I have a few general questions regarding using LVDS to drive an lcd panel... > From studying TMDS (DVI signal) and LVDS I have found they are quite similar. Is it p


LVDS on Drigmorn1

Started by John Adair in comp.arch.fpga10 years ago

In answer to all of you who asked about LVDS support on Drigmorn1 we believe 2 pairs of LVDS are very viable but as yet have not tested...

In answer to all of you who asked about LVDS support on Drigmorn1 we believe 2 pairs of LVDS are very viable but as yet have not tested the feature. Some others may be possible but pin routing is not so good. John Adair Hone of Drigmorn1. The low cost starter FPGA development board.


electrical interface problem LVPECL - LVDS multi-inputs

Started by Kurt Kaiser in comp.arch.fpga11 years ago 4 replies

Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my...

Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my FPGA. The FPGA features 2 LVDS interfaces, whereas each LVDS pair is located at opposite sides of the device, meaning there will be some extensive routing to do. I designed a resistor network for the level conversion from LVPECL to LVDS. What I'd li...


LVDS problem - Black magic anyone?

Started by Anonymous in comp.arch.fpga3 years ago 13 replies

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. On= ly 6 wirea are...

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. On= ly 6 wirea are used: GND + Power LVDS (with embedded clock), 720Mbps UART (Rxd + Txd) (The cable is unshielded for flexibility reasons) The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is unus= ed, one pair is LVDS, one pair is GND + Rxd and...