electrical interface problem LVPECL - LVDS multi-inputs

Started by Kurt Kaiser in comp.arch.fpga15 years ago 4 replies

Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my...

Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my FPGA. The FPGA features 2 LVDS interfaces, whereas each LVDS pair is located at opposite sides of the device, meaning there will be some extensive routing to do. I designed a resistor network for the level conversion from LVPECL to LVDS. What I'd li...


LVDS for lcd panel and RocketIO

Started by in comp.arch.fpga17 years ago 4 replies

Hi, I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade...

Hi, I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade -5. Do I have to get into the RocketIO stuff now, or does it have nothing to do with it? regards, Benjamin


Spartan 3e, LVDS LCD.

Started by News in comp.arch.fpga13 years ago 2 replies

Greetings, I'll start with my apologizes for being a complete newbie to the fpga world. I've acquired a spartan 3e starter board, and have...

Greetings, I'll start with my apologizes for being a complete newbie to the fpga world. I've acquired a spartan 3e starter board, and have completed some of the simpler tasks on fpga4fun.com. I am looking for some guidance on how to implement LVDS to control a LCD panel. I have the docs on the panel, it is a 1366 x 768 40" LCD from a tv. It uses 4 lvds pairs @ 80 mhz. I have the...


Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!

Started by Anonymous in comp.arch.fpga10 years ago 1 reply

HI Folks; I've been asked to design a VITA57 board. I need to loop back all LA and HA signals as 2.5 volt LVDS. My customer has given...

HI Folks; I've been asked to design a VITA57 board. I need to loop back all LA and HA signals as 2.5 volt LVDS. My customer has given me the following requirements: Carrier board has 144 bidirectional signals configurable as both LVDS xmitters and LVDS receivers. They want to loop back 72 signals as Soource synch. xmitters tied to the other 72 as receivers.Then they want to fli...


ISERDES2 divide factor

Started by jonpry in comp.arch.fpga5 years ago 3 replies

Hi all, I have a Spartan-6 LX45 board with a whole bunch of lvds going in and out at a rate of 780mbps. After running out of pins I was...

Hi all, I have a Spartan-6 LX45 board with a whole bunch of lvds going in and out at a rate of 780mbps. After running out of pins I was forced to put two lvds receiving pairs into a different bank from the rest of the bus. To make matters worse this bank has an active MCB. All of the tx/rx lvds is synchronous with a clock I have inside the fpga so both transmit and receive are handled ...


Re: LVDS in Xilinx (Spartan-3)

Started by Jon Elson in comp.arch.fpga18 years ago 3 replies

Jason Daughenbaugh wrote: > Hello all, > > I am considering using the LVDS mode in spartan-3 FPGAs to run > offboard via a cat-5 RJ-45...

Jason Daughenbaugh wrote: > Hello all, > > I am considering using the LVDS mode in spartan-3 FPGAs to run > offboard via a cat-5 RJ-45 connector. We have been doing this for a > long time with LVDS parts from TI and National, but using the FPGA > directly would be a cost savings (but also require a lot of pins!) > > I am concerned about exposing these I/O pins this way, I feel much > safe


Can Spartan-6 Support M-LVDS ?

Started by ajpanicker in comp.arch.fpga12 years ago 2 replies

Does the Spartan-6 LX family or Spartan3A support the Multipoint-LVDS specifications? We need input and ouput buffers compliant to M-LVDS...

Does the Spartan-6 LX family or Spartan3A support the Multipoint-LVDS specifications? We need input and ouput buffers compliant to M-LVDS type1 and types 2. Also , the buffers should be 5V LVTTL tolerant.


Semi-OT: LVDS and Cold Sparing

Started by rk in comp.arch.fpga16 years ago 2 replies

Hi, Don't happen to have an LVDS specification (EIA-644) handy and couldn't find a freebie on the www. So hopefully someone out there has...

Hi, Don't happen to have an LVDS specification (EIA-644) handy and couldn't find a freebie on the www. So hopefully someone out there has one. Here's the question, I was told that section 4.4.2, & 6 have the fail-safe requirements. The issue is whether cold sparing capability is an LVDS requirement. I don't recall it being a requirement but I do want to go to the documentation to ...


Interfacing Cyclone III to 3.3v LVDS devices

Started by liqi...@gmail.com in comp.arch.fpga14 years ago 3 replies

How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks

How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks


Re: LVDS output pins of Altera Cyclone II

Started by only...@online.ms in comp.arch.fpga15 years ago 1 reply

Hi Rob, I know that I have to use the assigment editor to change the output type from LVTTL (default) to LVDS. But when using LVTTL I...

Hi Rob, I know that I have to use the assigment editor to change the output type from LVTTL (default) to LVDS. But when using LVTTL I always have access to the "output enable" of the output pin to tri- state the pin. But this does not work when using LVDS output. The output register is always enabled (OE set to '1') when I look at the design with the RTL viewer. This is a little ...


drive LVDS clocks with a spartan3

Started by Julien Lochen in comp.arch.fpga15 years ago 1 reply

Hello, I work as Design Engineer at Bull SAS in France (Server Design and Development). I saw a webcase on the web in which someone try to...

Hello, I work as Design Engineer at Bull SAS in France (Server Design and Development). I saw a webcase on the web in which someone try to provide some guidance concerning LVDS signals. I am not sure to have understood all your answers, so please let me ask the following question : I am currently working on a design based on the spartan XC3S1000. Can it be used to drive LVDS clocks ...


Fully Comitted to LVDS as Comparitors

Started by gnua...@gmail.com in comp.arch.fpga11 months ago

I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a...

I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a comparator. So I'm pretty committed to this working. The LVDS common mode range can work down to 50 mV and I"ll be testing that. I need to sense the voltage across a FET in an H bridge for over current or open load. The ADCs need to have decen...


LVDS pin placing on CYCLON II problem

Started by in comp.arch.fpga14 years ago 3 replies

Hi, I'm working on design with LVDS signals and when I'm trying to place LVDS inputs at dedicated pins I got : Error: Non-differential I/O...

Hi, I'm working on design with LVDS signals and when I'm trying to place LVDS inputs at dedicated pins I got : Error: Non-differential I/O pin addr[8] in pin location 86 and pad 103 too close to differential I/O pin clk_pll(n) in pin location 90 and pad 107 -- pins must be separated by a minimum of 4 pads And I don't know why ? How can it be too close ? Is any workaround for th...


LVDS output pins of Altera Cyclone II

Started by only...@online.ms in comp.arch.fpga15 years ago 1 reply

Hi, does anybody know how to switch of the LVDS output pins of a Cyclone II? I use the "alt_lvds" megafunction but there are no inputs to...

Hi, does anybody know how to switch of the LVDS output pins of a Cyclone II? I use the "alt_lvds" megafunction but there are no inputs to this megafuction to enable or disable the LVDS output pins. I thought about writing my own serializer as a workaround but I have no idea how this is done. But it should be possible by using the double data rate IOs and some shift registers. T...


xilinx spartan 6 deserialization

Started by Serkan in comp.arch.fpga11 years ago 1 reply

I just have 1 fast LVDS data line. I need to have 10 bits of data in a register , every 5 clock cycles(DDR), coming from only...

I just have 1 fast LVDS data line. I need to have 10 bits of data in a register , every 5 clock cycles(DDR), coming from only 1 differential data line. Dear Gurus, 1- Can I deserialize a 240 Mhz , LVDS, DDR input coming data using a 10:1 serdes ratio. (clk is also LVDS) 2- I want to do it with data width = 1( D = 1), is it possible? 3- Do I have to put delay to clk inputs. If ...


Single ended LVDS into FPGA

Started by Nico Coesel in comp.arch.fpga12 years ago 5 replies

Some food fo thought: I'm working on a new design in which I need to bring 64 LVDS (250Mbps each/ 125MHz fmax) lines into a Spartan3 FPGA. The...

Some food fo thought: I'm working on a new design in which I need to bring 64 LVDS (250Mbps each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between the source and the FPGA is less than 2" / 5cm. Ofcourse there is a solid ground plane underneath the signals (the board will have at least 4 layers). I'm wondering if I can save a lot of pins if I feed the LVDS signals single end...


LVDS Input buffer in VHDL (ISE)

Started by Roger in comp.arch.fpga16 years ago 9 replies

I'm trying to instantiate some LVDS input buffers in VHDL using the following code: LVDS_lines: for i in 0 to 19 generate ...

I'm trying to instantiate some LVDS input buffers in VHDL using the following code: LVDS_lines: for i in 0 to 19 generate Inputs_LVDS : IBUFDS_LVDS_25_DT -- LVDS input buffer with Rterm active port map ( I => data_lvds_in_p(i), IB => data_lvds_in_n(i), O => data_lvds_in_sig(i)); end generate; but ISE doesn't seem to recognise IBU


clock timing

Started by in comp.arch.fpga16 years ago 15 replies

Hi, I am driving a LCD display with a pixel clock of 66 MHz. The pixels are stored in a fifo, for parallel to lvds conversion I use an...

Hi, I am driving a LCD display with a pixel clock of 66 MHz. The pixels are stored in a fifo, for parallel to lvds conversion I use an external IC, because my Virtex2 has a to small speed grade to do lvds directly. I generate my pixel_clk with a dcm. Then I have lvds_clk


Interconnecting 3v3 LVDS transmitter to 2V5 Receiver

Started by saijayram in comp.arch.fpga12 years ago 2 replies

Hi. Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..? I am using cyclonII fpga for a receiver in which LVDS inputs are...

Hi. Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..? I am using cyclonII fpga for a receiver in which LVDS inputs are connected to 2V5 powered bank. will the FPGA be damaged with such interconnection..? I am using these lines for clock (26MHz) interconnecting two boards separated by a distance of 6 inches thru mother board. Thank you in advance sai


Need support for LVDS to Tmds translation on altera device

Started by morp in comp.arch.fpga12 years ago 1 reply

Hi, I've been wondering how to translate lvds drive to tmds, my application is chip to chip only, i.e tmds does not go through any cable...

Hi, I've been wondering how to translate lvds drive to tmds, my application is chip to chip only, i.e tmds does not go through any cable etc. From altera fpga, the lvds (translated into tmds) goes to a tmds input chip. What could be a solution for this? thanks.