Chip to Chip LVDS

Started by yy in comp.arch.fpga15 years ago 6 replies

Hi i'm currently working on a high-speed chip-to-chip serial interface FPGA interface, i would like to know some suggestions regarding...

Hi i'm currently working on a high-speed chip-to-chip serial interface FPGA interface, i would like to know some suggestions regarding FPGA differential signalling; especially the trace matching of pair of LVDS signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, Tx_Data) etc. My application is for 622Mbps signalling rate. Anyone has an experience on this?


Maximum LVDS-rate of Spartan 3E

Started by Thomas Entner in comp.arch.fpga17 years ago

Does anybody know the maximum LVDS-rate of Spartan 3E? I did not find anything in the datasheets, while the Spartan-3 datasheets says 622 Mb/s...

Does anybody know the maximum LVDS-rate of Spartan 3E? I did not find anything in the datasheets, while the Spartan-3 datasheets says 622 Mb/s IO transfer-rate (I think this is valid for LVDS). As we know our friends at X & A, when a nice high number gets quietly removed from the feature-list on the front page of the data-sheet, there is a reason for it... Or was I maybe just blind? ...


LVDS through connectors

Started by Georgi Beloev in comp.arch.fpga17 years ago 12 replies

Hi all, I'm designing a system in which a 4-bit + clock LVDS point-to-point bus has to connect two FPGAs. The two FPGAs are on two different...

Hi all, I'm designing a system in which a 4-bit + clock LVDS point-to-point bus has to connect two FPGAs. The two FPGAs are on two different boards--one is on a mainboard and the other is on a plug-in board. What kind of board-to-board connector is recommended for high-speed (~400 Mbps) LVDS signals? Connector parameters to look for? Signal integrity issues? Board layout with regard ...


Xilinx Virtex II fpga - providing single ended signal to lvds defined pin

Started by TD in comp.arch.fpga16 years ago

Hello, I am having ADI board containing xilinx virtex II chip. There are two pins defined as LVDS_33 I/O but I wanted to reprogram them...

Hello, I am having ADI board containing xilinx virtex II chip. There are two pins defined as LVDS_33 I/O but I wanted to reprogram them as single ended signals and hence I had removed the 100ohm resistance between the lvds signals. The lvds receiver output signals are ignored by my design. Hence I am sending two single ended signals to the two pins which are defined as lvds. Now the 2 pins...


Require a solution - LVDS support +RJ45 connectors

Started by sharath20284 in comp.arch.fpga12 years ago 2 replies

Hello, I am not sure if this post is in the right place - I hope to get some help I am looking for a PCI/e based FPGA solution - The board...

Hello, I am not sure if this post is in the right place - I hope to get some help I am looking for a PCI/e based FPGA solution - The board should be able to support LVDS with 2 RJ45 i/o ports which connect to CAT5 cables. I plan to implement SPI signal on the FPGA and send the generated signal over LVDS. I am looking for a hardware solution for this. Can you please point to me viable opti...


Starting with LVDS

Started by Frank Schreiber in comp.arch.fpga16 years ago 14 replies

Dear all I'm starting with LVDS. My task is sending 8-bits signal to LVDS Transmitter port on my board. I declared a 8 bits vector, assigned...

Dear all I'm starting with LVDS. My task is sending 8-bits signal to LVDS Transmitter port on my board. I declared a 8 bits vector, assigned pins, and changed values in 8-bits signal, but nothing happended in my oscilloscope. Assume that pins-out are right assigned, all wires and DAC are working perfectly. Can anyone advise me, how to make it works. Many thanks Frank


Serial LVDS ADC to spartan6

Started by Thomas Heller in comp.arch.fpga9 years ago 2 replies

I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a...

I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a single HDMI connector for this. The converters I'd like to use are the ADS6224 or ADC12S105, running at 100 MHz sample rate. They have 6 data LVDS data outputs: 4 data lines, 1 frame clock and 1 bit clock. Since the HDMI connection only has 5 differ...


hot- or cold-plugging altera cyclone-3 LVDS inputs causing damage?

Started by BW in comp.arch.fpga11 years ago 2 replies

Hi! We have a design where an Altera Cyclone-3 (EP3C5) with LVDS inputs is connected to a sender on another board through a cable. In a...

Hi! We have a design where an Altera Cyclone-3 (EP3C5) with LVDS inputs is connected to a sender on another board through a cable. In a number of cases on our prototype boards, the LVDS-inputs have been fried from this setup. Apart from any misdesign in the sender-board, does anyone have any suggestions on possible causes? Do these inputs have lesser ESD- protection? The cables used a...


Driving a 30 bit wide LVTTL bus at 160MHz

Started by Dolphin in comp.arch.fpga15 years ago 6 replies

Hello, In my future design I could win a lot of pins if I could drive a bus at 160MHz. Because of bank restrictions and because this bus is...

Hello, In my future design I could win a lot of pins if I could drive a bus at 160MHz. Because of bank restrictions and because this bus is connected to a CPLD, I will have to use LVTTL. Has anybody tried driving a bus in LVTTL at 160MHz? I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has LVDS CPLDs but only the large CPLDs support LVDS inputs. I am afraid that th...


Lvds input problem urgent

Started by Dan in comp.arch.fpga17 years ago 1 reply

I have 2 signals that come from an lvds transmitter sources: lvds1p, lvds1n. I use an cyclone EP1C6. I want to put these signals on pins 124...

I have 2 signals that come from an lvds transmitter sources: lvds1p, lvds1n. I use an cyclone EP1C6. I want to put these signals on pins 124 and 123. how can i make this and how a can use after that this signal in my design (transmitter -> lvds1p,lvds1n -> fpga:receive these signals -> how can i group then in signal lvds and the use this final signal ????) I use Quartus4.1 Than


Using LVDS Input for Delta Sigma ADC

Started by rickman in comp.arch.fpga9 years ago 6 replies

I found an app note on the Lattice site about using the LVDS input as the input comparator. My design is very low power and I am concerned...

I found an app note on the Lattice site about using the LVDS input as the input comparator. My design is very low power and I am concerned about the power consumption of this input. Typically inputs are not supposed to operate in the linear region as this draws extra power in a "shoot through" mode. The LVDS spends its entire time in this region. Will this cause the power consumption...


LVDS i/o in a SystemVerilog Interface block

Started by fpgabuilder in comp.arch.fpga12 years ago 2 replies

I need to instantiate LVDS interfaces in my top-level. I am planning to use SV interface blocks. Altera's documentation suggests that...

I need to instantiate LVDS interfaces in my top-level. I am planning to use SV interface blocks. Altera's documentation suggests that LVDS i/os should only be instantiated using a megafunction. But the interface blocks do not allow hierarchy so I cannot instantiate a megafunction inside the interface block. Any thoughts on this?


Xilinx LVDS

Started by Anonymous in comp.arch.fpga16 years ago 6 replies

Hi, I want to findout the minimum accepted voltage difference for LVDS in Xilinx Spartan3 FPGAs. For example is 40mV acceptable? Many...

Hi, I want to findout the minimum accepted voltage difference for LVDS in Xilinx Spartan3 FPGAs. For example is 40mV acceptable? Many thanks for the help in advance.. H aka N


Xilinx LVDS termination resistor

Started by Brad Smallridge in comp.arch.fpga16 years ago 4 replies

How do you turn the 100 ohm resistor on for an LVDS input? I am using the HDR2 header on an ML402 dev board. Brad Smallridge aivision.com

How do you turn the 100 ohm resistor on for an LVDS input? I am using the HDR2 header on an ML402 dev board. Brad Smallridge aivision.com


Bidirectional LVDS

Started by Richard Henry in comp.arch.fpga15 years ago 14 replies

I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with serial/ deserializer pairs...

I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with serial/ deserializer pairs at each end might work. Does anyone have any experience or guidance on such a setup?


Virtex 5 LVDS

Started by maxascent in comp.arch.fpga13 years ago 8 replies

Hi I am routing a pcb with some LVDS signals. Is there a way in Virtex 5 to invert the signal so that I can have P-> N and N-> P on the...

Hi I am routing a pcb with some LVDS signals. Is there a way in Virtex 5 to invert the signal so that I can have P-> N and N-> P on the pcb. Cheers Jon


FPGA on-die LVDS termination issues

Started by dc207 in comp.arch.fpga12 years ago 11 replies

Hello, We use several source-synchronous LVDS-based interfaces in several PCB designs, such as a unidirectional interface from several...

Hello, We use several source-synchronous LVDS-based interfaces in several PCB designs, such as a unidirectional interface from several multi-channel ADC devices (TI ADS725x) towards FPGA (Xilinx Virtex4 family, SX subfamily), or a full-duplex interface between high-end DSP devices (ADI ADSP-TS201S) and FPGA (Xilinx Virtex4 family, FX subfamily). In both mentioned cases, we use on-die LVDS term...


DSP-PC architectural advice needed.

Started by soos in comp.arch.fpga17 years ago 4 replies

Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement it. Basically it's...

Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement it. Basically it's an ADC connected to the TS201 that sends the entire information sampled to a PC through one of it's LVDS connectors. On the PC there is a PCI Card that knows how to do LVDS for example the PCI GP-ECL/SSD16. of the EDT group. Before checking all the car...


Is Spartan 6 good for this project?

Started by Indie Tinde in comp.arch.fpga11 years ago 3 replies

I'm new in FPGA field, so i have a problem.... I need a low cost FPGA able to drive a sensor with 5 LVDS DDR data sensor-> FPGA 1 LVDS Clock...

I'm new in FPGA field, so i have a problem.... I need a low cost FPGA able to drive a sensor with 5 LVDS DDR data sensor-> FPGA 1 LVDS Clock at 300MHz sensor-> FPGA 1 LVDS Clock at 300Mhz FPGA-> sensor SPI FPGA-> sensor in sensor evaluation board, a Virtex5 XC5VLX50T-1FFG1136C is used. I need a low cost fpga, so i thought about Spartan6 family (for example XC6SLX150T-3FGG676C). What do you


requirements to select FPGA using LVDS

Started by prav...@gmail.com in comp.arch.fpga16 years ago 2 replies

hi all, wat all the basic requirements needed to be analysed before selecting a FPGA chip for using high speed LVDS. thanks in advance praveen

hi all, wat all the basic requirements needed to be analysed before selecting a FPGA chip for using high speed LVDS. thanks in advance praveen