FPGA board with High Speed LVDS

Started by mk in comp.arch.fpga16 years ago 2 replies

Hi, I am looking for a board with at least 16 balanced LVDS connections able to run at 800 MHz, preferably A but X would be OK too. Any and all...

Hi, I am looking for a board with at least 16 balanced LVDS connections able to run at 800 MHz, preferably A but X would be OK too. Any and all suggestions are welcome. Of course the larger the FPGA the better, and two or more FPGAs would be awesome :-) Thanks.


LVDS

Started by maxascent in comp.arch.fpga16 years ago 3 replies

I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying to match the length of the signals. Will I be ok to match them to...

I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying to match the length of the signals. Will I be ok to match them to within 1mm. The max length of any signal will be 33mm and the adc is clocked at 250MHz. Thanks Jon


FPGA LVDS for AC-decoupled transmit over CAT-5 cable

Started by Antti in comp.arch.fpga13 years ago 13 replies

if i think of it, it should be doable? but i do not recall any projects that would use such transmit method normal FPGA LVDS are fast enough...

if i think of it, it should be doable? but i do not recall any projects that would use such transmit method normal FPGA LVDS are fast enough that it would be possible just capacitive decoupling sure some encoding should be applied but that shouldnt also be a problem Antti


Spartan-3 (XC3S400) DDR LVDS support?

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

What Mbps speed does DDR LVDS serializer in XC3S400 transmission support? (for use with TFT screens or backplane)

What Mbps speed does DDR LVDS serializer in XC3S400 transmission support? (for use with TFT screens or backplane)


Cyclone Board with // LVDS lines

Started by Keith Williams in comp.arch.fpga17 years ago 1 reply

Hi! I've already googled and dug through several online lists of FPGA boards, but haven't found what I'm looking for, yet. I'm needing a...

Hi! I've already googled and dug through several online lists of FPGA boards, but haven't found what I'm looking for, yet. I'm needing a Cyclone board that has at least 32 LVDS I/O pins available (and terminated). With at least one PLL available to be driven from an external source. Target price of less than $500 U.S. Thanks, Keith


LVDS in cyclone

Started by Eduard Nikke in comp.arch.fpga18 years ago 1 reply

Hi, Can someone help me with this issue. I am looking to build a serialer in a FPGA. Base frequence is 72MHz - 7 bits serialiser - so I...

Hi, Can someone help me with this issue. I am looking to build a serialer in a FPGA. Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of 504MBps. I thought this wat not possible in a Cyclone device but just reads the app. note and it seems to be possible. I have only some strong concerns because there is no timing budget and the IOB are not DDR IOB blocks. ...


LVDS without termination

Started by Kolja Sulimma in comp.arch.fpga17 years ago 21 replies

Austin Lesea wrote at 2003-10-02 08:03:57 PST "Also look at what happens when you do not have a 100 ohm termination. For some signals, and...

Austin Lesea wrote at 2003-10-02 08:03:57 PST "Also look at what happens when you do not have a 100 ohm termination. For some signals, and lengths of pcb, it may not be required." and "If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few signals." I need to get 16 LVDS pairs into one edge of a Spartan-3. This is really simple to layout without termination resistors and re...


Specifying LVDS I/O's in Xilinx FPGA's

Started by Anonymous in comp.arch.fpga14 years ago 4 replies

Hi, Can someone please point me in the right direction. I attempted to define my LVDS inputs via the UCF file for my Xilinx spartan...

Hi, Can someone please point me in the right direction. I attempted to define my LVDS inputs via the UCF file for my Xilinx spartan xc3s1500. NET data_in LOC = F19 | IOSTANDARD = LVDS_25 ; the Xilinx answer record impies that this will work OK. http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187 Unfortunately I get the following warning, and the in...


Connecting different FPGAs using LVDS

Started by Enes ERDIN in comp.arch.fpga14 years ago 5 replies

Hi, I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good signal however...

Hi, I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good signal however on Chipscope I see glitches. I am trynig to operate at about 1 MHz. For VirtexE side there is a 100 ohm termination resistor between differential lines at the receiver and there are 160 ohms and a 140 ohm at the transmitter sides and the connecting cable is ...


Spartan-3 LVDS driving TFT LCD panel..?

Started by Mike Harrison in comp.arch.fpga16 years ago 6 replies

Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link I think) direct from the S3 I/Os ? If so,...

Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention recently about using the DDR registers to reduce the data rate but couldn't immediately see any Xilinx appnotes when I had a quick look. Also, as the IO banks on the lower-end dev boards tend...


1250gbps input on virtex-5

Started by Kolja Sulimma in comp.arch.fpga14 years ago 6 replies

Hi, we need to input a continous stream of 32 LVDS data bits at 1.25gbps per pin into a Virtex-5. There is a clock provided for each byte...

Hi, we need to input a continous stream of 32 LVDS data bits at 1.25gbps per pin into a Virtex-5. There is a clock provided for each byte (source synchronous). There was a news item by Xilinx that says this is possible. But how many loops do I need to jump through to make it work? - What speedgrade do we need? - Is there a difference in timing between LXT, FXT and SXT for LVDS input...


FPGA or CPLD?

Started by Sink0 in comp.arch.fpga11 years ago 11 replies

Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could not find any driver that could be placed to run that multdrop network...

Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could not find any driver that could be placed to run that multdrop network (any protocol and datalink designed with small and size variable packet (Max 256 bytes) would be suitable) i designed one myself on a FPGA. On the on the uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the clock is recovered with oversa...


VirtexE LVDS driver

Started by Enes ERDIN in comp.arch.fpga14 years ago 1 reply

Hi to all, I am confused about one thing that if I want to use LVDS in VirtexE, should I feed the Vcco of the desired bank with 2.5 V. Is...

Hi to all, I am confused about one thing that if I want to use LVDS in VirtexE, should I feed the Vcco of the desired bank with 2.5 V. Is it applicable if I feed the bank by 3.3 V? What about playing with the termination resistors? I couldn't find a satisfactory answer through searching but only XAPP232 Appendix A was a bit helping. Thanks in advance. Enes


Deserializing Camerlink on Spartan XC3s400

Started by Anonymous in comp.arch.fpga13 years ago 4 replies

Good Morning, I need to de-serialize a camlink LVDS stream because my FPGA doesnt have enough pins to accept parallel from a DS90288 etc. and...

Good Morning, I need to de-serialize a camlink LVDS stream because my FPGA doesnt have enough pins to accept parallel from a DS90288 etc. and am looking for a push in the right direction in where to start. I realise i need to set the constraints file such that the pins are set for LVDS input, but I have no experience with constraints files, so a quick run-down or resource would be great....


LVDS PCI card is needed

Started by soos in comp.arch.fpga17 years ago 7 replies

Hello, As a part of a project I am looking for a FPGA on PCI that has 8 LVDS channels and the driver of this card that enables all the 8...

Hello, As a part of a project I am looking for a FPGA on PCI that has 8 LVDS channels and the driver of this card that enables all the 8 channels of read and write. Total data transfer capacity is 200-400 Mbps. Questions are: 1.Is this data rate achievable? 2.Can anyone point a solution for this design? Any help will be appreciated, Thanks in advance, Marc.


Virtex 4 Cameralink DCM Limitation

Started by ees3dc in comp.arch.fpga10 years ago 11 replies

I have a cameralink (LVDS SERDES) I'm trying to capture data with using a Virtex 4 mature product. I have ported the XAPP485 deserializer using...

I have a cameralink (LVDS SERDES) I'm trying to capture data with using a Virtex 4 mature product. I have ported the XAPP485 deserializer using V4 primitives (slightly different to Spartan3A) and configured the DCM to run at 32MHz. The problem is the LVDS-TTL receivers on the PCB cannot run at the 32MHz x7 rate. The slow risetime means I hardly see a 2V '1' threshold in the Xilinx. I theref...


Virtex-4 Vicm for LVDS with Vcco = 3.3V.

Started by Symon in comp.arch.fpga16 years ago 2 replies

Hi All, So, it looks like it's OK for me to use an unterminated LVDS input on an I/O bank with Vcco = 3.3V. I even checked that the tools don't...

Hi All, So, it looks like it's OK for me to use an unterminated LVDS input on an I/O bank with Vcco = 3.3V. I even checked that the tools don't complain! Does anyone know of any data for Vicm (the common mode range) for these inputs? If the receivers are powered by Vccaux, I assume the spec is the same as for LVDS_25, otherwise maybe the spec scales with Vcco. TIA, Syms.


how can I improve my code?

Started by in comp.arch.fpga17 years ago 17 replies

Hi, since I am a beginner with fpgas and vhdl, I want to ask if some fpga-veteran can give me some hints how to improve my...

Hi, since I am a beginner with fpgas and vhdl, I want to ask if some fpga-veteran can give me some hints how to improve my coding-style. Attached is my latest code (for controlling an LCD via LVDS), it works in the simulator and is not yet tested on the chip. regards, Benjamin -- lvds_tick is a clock at 7x pixel-clock (140 MHz) -- lvds_clk is the clock for the lvds bus, same as p...


Connecting ADC chip to sparta 3 a dsp

Started by lakshmi3489 in comp.arch.fpga12 years ago 2 replies

hi there I have an ADC chip which is working in the LVDS mode. The data out(D0+,D0-,......D13+ and D13-),along with data...

hi there I have an ADC chip which is working in the LVDS mode. The data out(D0+,D0-,......D13+ and D13-),along with data clock out(DC0+,DC0-) and out of range(OUR) are connected physically to Sparta 3a dsp. My question is how do I directly collect these LVDS signals in my sparta 3a dsp core. How do I get back my data in aa format I can work on? ------------...


OFFSET Constraining a Signal behind a DCM?

Started by Christian Wiesner in comp.arch.fpga15 years ago

Hi, I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E. The clock from the ADC enters the FPGA via LVDS, gets...

Hi, I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E. The clock from the ADC enters the FPGA via LVDS, gets IBUFGDSed and enters the DCM. It leaves the DCM as CLOCK_0 and half the inputclock, CLOCK_DV. CLOCK_0 then clocks a IP-Core FIFO. Meanwhile, the DATA from the ADC (LVDS as well) enter the FPGA and are routed into the 8-bit input of the FIFO. There I wa...