Anybody have any experience with Altera Stratix 840 Mbps LVDS?

Started by Nate Goldshlag in comp.arch.fpga18 years ago 1 reply

Does anybody have any experience using many channels of 840 Mbps LVDS data using the Altera Stratix FPGA family? Any pitfalls to avoid...

Does anybody have any experience using many channels of 840 Mbps LVDS data using the Altera Stratix FPGA family? Any pitfalls to avoid or advice? Nate


Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)

Started by Sean Durkin in comp.arch.fpga14 years ago 2 replies

Hi *, since switching to ISE9.2, one of my favourite topics has come up again... Basically, what I have is an FPGA with a bank that has a...

Hi *, since switching to ISE9.2, one of my favourite topics has come up again... Basically, what I have is an FPGA with a bank that has a VCCO of 3.3V. This bank has several LVTTL outputs and a few LVDS25-inputs. At the time when the board was designed, this was a valid configuration: LVDS-input buffers are powered from VCCAUX, which is always 2.5V, so it doesn't matter what your VCCO on t...


interface ad9229 with altera stratix II

Started by michael in comp.arch.fpga15 years ago 1 reply

can some one give me a hint on how to interface AD9229 a to d converter with stratix II lvds interface? the AD9229 output sample word of 12...

can some one give me a hint on how to interface AD9229 a to d converter with stratix II lvds interface? the AD9229 output sample word of 12 bits, however the lvds serdes factor is 10 at the max. -thanks


Spartan-3 Serial LVDS max speed?

Started by Eric in comp.arch.fpga16 years ago

The Xilinx App Note, xapp224, suggests that it's possible to do non-source-synchronous data recovery in a spartan-3 at up to 320 Mbps (320 MHz)...

The Xilinx App Note, xapp224, suggests that it's possible to do non-source-synchronous data recovery in a spartan-3 at up to 320 Mbps (320 MHz) -- has anyone ever managed to get this or higher serial speeds working in a spartan-3 PQ208 package? I'm trying to make this work with a 100-ohm differential LVDS link and I can't seem to get my design up past 150 Mbps. I'm totally willing to enterta...


Clock Phase Fun on Cyclone III

Started by Rob Gaddi in comp.arch.fpga10 years ago 1 reply

I've got a project going on a Cyclone III, and have hit an issue that seems like it has a simple solution if only I already knew it. I've got...

I've got a project going on a Cyclone III, and have hit an issue that seems like it has a simple solution if only I already knew it. I've got a 125 MHz input clock (CLK125). I've got an ADC that takes in an LVDS 250 MHz clock (CLKOUT), and outputs 250 Msps parallel LVDS data, changing on the rising edge of a regenerated 250 MHz clock (CLKFB). The phase relationship of my FPGA to anyth...


How LVDS Drivers kills?

Started by Masoud Naderi in comp.arch.fpga18 years ago 5 replies

Dear all, Please tell me how LVDS drivers with cables can damaged? Possible cases are: 1 - Power supply under/overshoots. 2 - ESD on...

Dear all, Please tell me how LVDS drivers with cables can damaged? Possible cases are: 1 - Power supply under/overshoots. 2 - ESD on cables. 3 - Missing hot-plugging. e.g. connect GND, then signal, then power. 4 - Killer spikes on power supply rail or input/outputs. 5 - ? Regards.


Spartan3E - problem in creating LVDS DDR pads

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

Hi all, I am trying to create LVDS, bidirectional, DDR I/O pads in a Spartan-3E chip (xc3s500e). I've created an I/O pad in VHDL which...

Hi all, I am trying to create LVDS, bidirectional, DDR I/O pads in a Spartan-3E chip (xc3s500e). I've created an I/O pad in VHDL which simply instatiates and connects Xilinx library components: * IOBUFDS = bidirectional, differential I/O pad, * IDDR2 = S3E input DDR logic, * ODDR2 = S3E output DDR logic, Tri-State control is not DDR - I've added a simple FF instance. The pad ...


Spartan 3 LVDS

Started by Andrew Holme in comp.arch.fpga13 years ago 3 replies

Hi, I'm using the Spartan 3 XC3S400-TQ144. Does this device have internal 100-ohm termination for LVDS input pairs, or must I use an external...

Hi, I'm using the Spartan 3 XC3S400-TQ144. Does this device have internal 100-ohm termination for LVDS input pairs, or must I use an external 100-ohm resistor? When I designed my board, I assumed internal termination would be enabled automatically by instantiation of the IBUFGDS; but looking at my signal levels, although my board is working, I would say there is no termination. The on...


LVDS simulation in Hyperlynx

Started by maxascent in comp.arch.fpga11 years ago 1 reply

I am trying to run a Hyperlynx simulation for LVDS in a Spartan 6 FPGA. I would like to use the DCI termination but when I select this model...

I am trying to run a Hyperlynx simulation for LVDS in a Spartan 6 FPGA. I would like to use the DCI termination but when I select this model the simulation complains that it cant perform it because it cant model a series resistor at the receiver input. I assume this is something to do with the termination but I am not sure what I am supposed to do. Thanks Jon -------------------...


Unknown LVDS pinout order

Started by jorbedo in comp.arch.fpga12 years ago

Hi, I had been learning LVDS as a hobby but I'm having a hard time understanding the pinout orders. Right know I would like to know the precise...

Hi, I had been learning LVDS as a hobby but I'm having a hard time understanding the pinout orders. Right know I would like to know the precise order of the pinouts of an LCD panel (30 pin I-Pex connector) between the panel and the motherboard (Atom z520 Intel US15w chipset). MB and panel pics: http://www.flickr.com/photos/47170574@N08/ How can achieve this?, via software, oscilloscope, ...


Xilinx Spartan 3 LVDS Misbehaving

Started by Antonio Roldao Lopes in comp.arch.fpga16 years ago 1 reply

Greetings FPGA Group, I'm attempting to input an LVDS clock signal into a SoC design. This development is based on a NuHorizons SP3 board with...

Greetings FPGA Group, I'm attempting to input an LVDS clock signal into a SoC design. This development is based on a NuHorizons SP3 board with a Spartan-3 (xc3s1500-fg676-4). Although it supports primitives for input differential clock signals through the usage of, for example, the IBUFGDS_LVDS_25 component, when I do instantiate such blocks, Bitgen reports a couple of non-informative warn...


mixing LVDS data

Started by Herwin in comp.arch.fpga18 years ago 1 reply

Hello, I have a newbie problem that is probably easy to solve. I have 4 data streams entering Virtex II FPGA through LVDS standard...

Hello, I have a newbie problem that is probably easy to solve. I have 4 data streams entering Virtex II FPGA through LVDS standard (each stream is 4 wires, 2 clock and 2 data). This is fine as I am able to receive the signals each individually i.e. data from each stream is clock by only their respective clock and the data does not interact with each other. What I want to do is to tr...


[Xilinx 2VP] DDR + Differential Input

Started by I.U. Hernandez in comp.arch.fpga18 years ago 5 replies

Hi guys, It's been ages since I haven't posted anything here... Well, I have a problem trying to build a design: - 311 MHz LVDS clock to...

Hi guys, It's been ages since I haven't posted anything here... Well, I have a problem trying to build a design: - 311 MHz LVDS clock to IBUFGDS - to DCM - generates CLK0 to BUFG (rxclk0_311a_ig) - generates CLK180 to BUFG (rxclk180_311a_ig) easy so far... Data comes in as an LVDS differential nibble (or nybble :O) apologies from my Spanish-English), I am supposed to Double Data...


Raggedstone1 LVDS Oscillator

Started by John Adair in comp.arch.fpga15 years ago

For those of you that have been waiting for this module the LVDS oscillator module for our low cost Spartan-3 Raggedstone1 development board is...

For those of you that have been waiting for this module the LVDS oscillator module for our low cost Spartan-3 Raggedstone1 development board is now available. Details here http://www.enterpoint.co.uk/moelbryn/modules/ics8442.html. It is capable of generating 31.25MHz to 700MHz and can be programmed serially from the FPGA. We are fitting a 25MHz crystal currently but the module can use a cl...


Xilinx V4 LVDS

Started by Brad Smallridge in comp.arch.fpga16 years ago 12 replies

Hello, Having trouble with some LVDS signals coming from a Camera Link interface. I expect to see from steady signals coming from this line...

Hello, Having trouble with some LVDS signals coming from a Camera Link interface. I expect to see from steady signals coming from this line camera. DVAL=1. But it's not there. And the LVAL, line valid, only comes on for maybe one clock, and I expect it to come on for 2K clocks. I am using IBUFDS as inputs. The UCF file loc the pins but that is all. Do I need something more to drop t...


Differential terminations in Virtex2 Pro.Attempt II!

Started by Symon in comp.arch.fpga18 years ago 2 replies

Dear All, I'll phrase my questions differently from my last attempt! Q1. If I instantiate a 2.5V LVDS input with differential...

Dear All, I'll phrase my questions differently from my last attempt! Q1. If I instantiate a 2.5V LVDS input with differential termination in my design, e.g. LVDS_25_DT, then I power its VCCO with 3.3V, what happens? I think the input DC thresholds should stay the same, as they're powered from VCCAUX, but what about the termination impedance? Q2. If I instantiate a 2.5V LVDS outpu...


URGENT HELP NEEDED: LVDS

Started by GaLaKtIkUs™ in comp.arch.fpga15 years ago 5 replies

Hi everybody! I felt in a very strange situation: I'm working with an FPGA BOARD: -2 Virtex-4LX -1 Quick LVDS bus between the 2 FPGAs. -1...

Hi everybody! I felt in a very strange situation: I'm working with an FPGA BOARD: -2 Virtex-4LX -1 Quick LVDS bus between the 2 FPGAs. -1 INPUT from an external board. -1OUTPUT to the same external board. I use for these quick interfaces ChipSync (Local clocking ressources +ISERDES+OSERDES). When I make my tests for the internal bus (the connection between the 2 FPGAs) I have no probl...


Differential terminations in Virtex2 Pro.

Started by Symon in comp.arch.fpga18 years ago 9 replies

Hi All, I'll open a webcase too, but I'm posting in hope of a super quick answer! Here's my question:- V2P has on-chip differential...

Hi All, I'll open a webcase too, but I'm posting in hope of a super quick answer! Here's my question:- V2P has on-chip differential terminations for LVDS signals, e.g. LVDS_25_DT. See answer #17244. However, although 3.3V banks can support LVDS receivers, the terminated mode is not allowed. I quote:- "Requirement to Turn on the On-chip Input Differential Termination The VCCO of the ...


I think I fried my I/O bank... (virtex-E question)

Started by NotTooSmart in comp.arch.fpga18 years ago 1 reply

Quick question... I've been using a Virtex-E fpga on a development board that provides jumpers to connect or disconnect Vcco for each I/O bank. ...

Quick question... I've been using a Virtex-E fpga on a development board that provides jumpers to connect or disconnect Vcco for each I/O bank. Some of my inputs are LVDS, and one of my signal sources has LVDS output that swings up as high as ~2.4V at the highest. On one of my last test runs I accidentally left the Vcco jumper uninstalled for the IO bank that this device was connected to, m...


Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?

Started by Christian Wiesner in comp.arch.fpga15 years ago 2 replies

Hi, I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via LVDS. The data should...

Hi, I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via LVDS. The data should be captured an put into a blockram. The OFFSET IN constraint, which I want to meet, says, that the DATA should be available 0.97ns before the CLOCK. So far I have the data-lines into their IBUFDS (8 times) and into the data-input of the BRAM. Clock...