Is there any version of Aurora protocol which works with LVDS instead of MGTs?

Started by Massoud in comp.arch.fpga15 years ago

Hi All, I reviewed LocalLink and Aurora protocol and it does not specifically say anything about RocketIO tranceivers. So I assumed that it...

Hi All, I reviewed LocalLink and Aurora protocol and it does not specifically say anything about RocketIO tranceivers. So I assumed that it could be implemented by using LVDS pins when higher speeds are not necessary. But its IP just works with RocketIO. - I am wondering if it's possible to implement it with diferrential pins other than RocketIO? - Does anybody know another pr...


LVDS clock management

Started by vasile in comp.arch.fpga14 years ago 1 reply

Hi, I need a 1:8 (ok 1:10 is good too) differential LVDS clock driver with clock bank enable (individual clk enabling option for every...

Hi, I need a 1:8 (ok 1:10 is good too) differential LVDS clock driver with clock bank enable (individual clk enabling option for every output) and very good clock skew parameters. It seems there is an industrial standard of serial programmable 1:10 LVDSin/LVDSout buffer (STLVD111 or PCK2111, etc) but I dislike the serial programming. I need one with parallel enabling feature, being driven ...


200+ MHz through a SCSI cable

Started by in comp.arch.fpga17 years ago 9 replies

Hi, I am glad to tell you, that my LCD via LVDS works now :) However it works only up to a lvds clock rate of about 200 MHz. I am not sure...

Hi, I am glad to tell you, that my LCD via LVDS works now :) However it works only up to a lvds clock rate of about 200 MHz. I am not sure yet, if the 200 MHz limit originates from the fpga or the cable. Has anybody put more than 200 MHz through a 0,4m SCSI cable? What is approximately the frequency limit of the (50 pin) scsi connector on my board? (assuming my cable is perfect) ...


Altera Stratix II GX LVDS max speed

Started by lecr...@chek.com in comp.arch.fpga16 years ago 8 replies

I had spoke with Charley Pryor at Altera a few months back and had asked about running a 16-bit data bus into a Stratix II and what sort of...

I had spoke with Charley Pryor at Altera a few months back and had asked about running a 16-bit data bus into a Stratix II and what sort of speeds we could expext to run it at. He had made the statement that they had designs running in the 1GHz range and that they had some in-house designs running at 2GHz. Looking at the data sheets from Jan. 05. they show the LVDS only being rated to 840 M...


Problem with floating inputs on LVDS ports

Started by Magne Munkejord in comp.arch.fpga15 years ago 6 replies

Hello, I have a design with several LVDS transceivers. The design works well when all ports are connected but once some ports are unconnected...

Hello, I have a design with several LVDS transceivers. The design works well when all ports are connected but once some ports are unconnected I start receiving garbage from the floating inputs. I use the IBUFDS primitives with "DIFFTERM = TRUE" on a Viretx4 LX chip for input buffers. I have tried to use pullup- and pulldown constraints from Xilinx ISE constraints editor but then I get...


Determine latency of GTX links vs Aurora+LVDS

Started by Vivek Menon in comp.arch.fpga11 years ago 3 replies

I have a design partitioned over 2 FPGAs. I am trying to determine the bene= fits of selecting GTX links vs. LVDS to transfer the data between...

I have a design partitioned over 2 FPGAs. I am trying to determine the bene= fits of selecting GTX links vs. LVDS to transfer the data between FPGAs. =20 Target Device : xc6vlx550t Target Package : ff1759 Target Speed : -2=EF=BB=BF =20 Latency calculations: 1. GTX interface: The GTX transceiver is configured at 106.25 MHz with 20 b= its input. This means the bits are transmitted at bit...


Finding aligned clock transitions with state machine

Started by jag9624 in comp.arch.fpga13 years ago 9 replies

Hello Everybody ! I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter with a Virtex 4 FX12. What troubles me is the...

Hello Everybody ! I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter with a Virtex 4 FX12. What troubles me is the movement of data words from the slow system clock to the faster serializer clock (fast clock is multiples of slow clock). Since the clocks are phase aligned by the dcm, i don't see nescessity for using an async fifo, but i fail to find a simpler solution. ...


VIIPro on-chip LVDS termination

Started by Roger in comp.arch.fpga17 years ago 3 replies

As I understand it, the VIIPro devices have on-chip differential termination resistors which can be brought into play by selecting the...

As I understand it, the VIIPro devices have on-chip differential termination resistors which can be brought into play by selecting the XXX_LVDS_25_DT buffers. I've looked at several designs using VIIPro devices from different manufacturers but they all seem to use external 100R resistors to achieve LVDS termination. Can anyone tell me why this would be the case please? I thought the redu...


virtex-5 lvds termination issue?

Started by Muzaffer Kal in comp.arch.fpga13 years ago 6 replies

Hi, I've been working on a high speed ADC board which has a LVDS outputs connected to a virtex-5 lx 50. The ADC board has 100 ohm...

Hi, I've been working on a high speed ADC board which has a LVDS outputs connected to a virtex-5 lx 50. The ADC board has 100 ohm differential lines but no receiver termination so I configured the IOs on the FPGA side to be LVDS_25 with DIFF_TERM option on. I connected the ADC board to the FPGA board and did a capture with a chipscope block and the data was what we'd expect. The problem star...


Xilinx PLB RapidIO LVDS Core

Started by Kevin Shaw in comp.arch.fpga18 years ago

Anyone out there using the PLB RapidIO LVDS core in the Xilinx EDK? If so, have you been able to transmit a packet (NREAD) successfully? I've...

Anyone out there using the PLB RapidIO LVDS core in the Xilinx EDK? If so, have you been able to transmit a packet (NREAD) successfully? I've been able to successfully complete training mode and the Error and Status CDR shows the "Port OK" but sending an NREAD packet results in the CSR indicating "Output Error - Encountered". Any help would be appreciated. Thanks, Kevin


Cheap Altera dev board with LVDS-compatible connector?

Started by Allan Wang in comp.arch.fpga11 years ago 5 replies

I'm looking for a cheap Altera dev board with DDR RAM and an LVDS compatible connector. However, it seems like the cheapest one is the $1000...

I'm looking for a cheap Altera dev board with DDR RAM and an LVDS compatible connector. However, it seems like the cheapest one is the $1000 "Cyclone III FPGA Development Kit". I initially thought that the $200 "Cyclone III FPGA Starter Kit" would work since it has HSMC, but the manual states that it is only intended for CMOS signals and has no provisions for differential pairs. So does ...


information required

Started by Anonymous in comp.arch.fpga19 years ago 2 replies

Hi everyone,        Iam an student having doubt in LVDS communication, Let say xilinx vertex FPGA is used for this pupose. ...

Hi everyone,        Iam an student having doubt in LVDS communication, Let say xilinx vertex FPGA is used for this pupose.        I have LVDS transmitter and receiver, No AC coupling is been used between them. Let say transmitter is in one board and receiver is in another board connected through bac


Digitally Controlled Impedance with Lattice ECP2M FPGA's

Started by JSalk in comp.arch.fpga15 years ago 2 replies

Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 lane...

Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 lane PCIe digitiser card with the National 500MSPS ADC and the ECP2M FPGA. The ADC output 32 pair LVDS and I have read the FPGA datasheet but there is no mention of DCI?? Thanks slkjas


Difference between BUFGDS and IBUFDS on clocks

Started by g. giachella in comp.arch.fpga17 years ago

Dear all, I'm a little bit confused about the usage of IBUFGDS and IBUFDS. In my design (on a XC2V8000 fpga) I have to acquire LVDS input data...

Dear all, I'm a little bit confused about the usage of IBUFGDS and IBUFDS. In my design (on a XC2V8000 fpga) I have to acquire LVDS input data using a LVDS clock which comes from an external board. It is not really clear to me which is the best between these 2 options 1) use IBUFGDS on clock and then drive a BUFGMUX 2) use IBUFDS on clock and then drive a BUFGMUX Data input goes to IBU...


Xilinx LVDS and SCSI

Started by Lucas in comp.arch.fpga17 years ago 1 reply

Hi, I want to implement a SCSI Ultra-160 or SCSI Ultra-320 host on a VirtexII-Pro FPGA. My goal is to connect the FPGA to an array of SCSI...

Hi, I want to implement a SCSI Ultra-160 or SCSI Ultra-320 host on a VirtexII-Pro FPGA. My goal is to connect the FPGA to an array of SCSI disks. This is proprietary link so I don't need full adherence to the specifications. My questions are: 1- Is Xilinx LVDS I/O compatible to the SCSI LVD standard? 2- Is it possible to implement a LVD Multidrop SCSI bus with a VirtexII-Pro FPGA? T...


serial protocol specs and verification

Started by alb in comp.arch.fpga8 years ago 41 replies

Hi all, I have the following specs for the physical level of a serial protocol: > For the communication with Frontend asynchronous LVDS...

Hi all, I have the following specs for the physical level of a serial protocol: > For the communication with Frontend asynchronous LVDS connection is used. > The bitrate is set to 20 Mbps. > Data encoding on the LVDS line is NRZI: > - bit '1' is represented by a transition of the physical level, > - bit '0' is represented by no transition of the physical level, > - insertion of an addit


Xilinx LVDS_25_DT termination issues????

Started by John Providenza in comp.arch.fpga18 years ago 5 replies

I'm doing a high speed design with 800 MHz LVDS data input into a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input termination mode for...

I'm doing a high speed design with 800 MHz LVDS data input into a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input termination mode for the LVDS standard and looked at the Xilinx Answer Record 17244 for further info. It sounds like this mode may not have the issues that DCI had. Does anyone know of any issues with using this input termination mode? Thanks! John Providenza ...


Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?

Started by Barry in comp.arch.fpga14 years ago 6 replies

To avoid going to a larger package, I want to mix LVDS_25 inputs with LVCMOS33 in the same I/O bank, with VCCO = 3.3V. I would also like to use...

To avoid going to a larger package, I want to mix LVDS_25 inputs with LVCMOS33 in the same I/O bank, with VCCO = 3.3V. I would also like to use the DIFF_TERM attribute on the LVDS inputs, to avoid external resistors, for better signal integrity and PCB routing. But apparently the LVDS differential termination uses VCCO, so it is required to be 2.5V with this attribute. Do I have any option...


Virtex 5 I/O

Started by maxascent in comp.arch.fpga12 years ago 1 reply

I have a pcb with a Virtex 5 and a programmable clock generator. I want to use an LVDS clcok signal from the clock gen to the fpga. The...

I have a pcb with a Virtex 5 and a programmable clock generator. I want to use an LVDS clcok signal from the clock gen to the fpga. The problem is that the clock generators default output is two 3.3V signals. The fpga bank is connected to 1.8V. I would like to know if this will be a problem having a 3.3V signal going to a 1.8V bank. Once I have programmed the clock to be LVDS output it should ...


LVDS termination scheme to nonstandard ribbon cable

Started by Anonymous in comp.arch.fpga15 years ago 42 replies

Hi I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat) cable with a characteristic impedance of 173R balanced...

Hi I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat) cable with a characteristic impedance of 173R balanced (103R unbalanced). I have tried xilinx webcase to answer on the termination requirements of LVDS for spartan 3 withhout much luck. I got 2 different answers. My questions are: 1) Can I use a ribbon cable with 173R balanced characteristic impedance? I have r...