Lattice Semi

Started by Colin Hankins in comp.arch.fpga10 years ago 23 replies

Has anyone worked with the Lattice Semiconductor ECP2M series of FPGA? Were the parts easy to get? Also, how is the ispLever design software...

Has anyone worked with the Lattice Semiconductor ECP2M series of FPGA? Were the parts easy to get? Also, how is the ispLever design software from Lattice? I've worked exclusively with Xilinx FPGAs and am looking for some feedback about what else is out there. My particular interest developed in the Lattice ECP2M because I need a FPGA/SERDES combo and the price for the ECP2M seems unbe...


Blog from Lattice Semiconductor

Started by MK Wong in comp.arch.fpga11 years ago

Hi there, I found one blog which is written by Lattice's staff. It sounds like a "un-official" channel to provide feedback or ask question to...

Hi there, I found one blog which is written by Lattice's staff. It sounds like a "un-official" channel to provide feedback or ask question to Lattice. Here is the URL. http://www.latticeblogs.typepad.com/ Have fun. MK


How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?

Started by Ssa in comp.arch.fpga10 years ago 1 reply

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what...

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what about the JTAG-debug unit? It seems to use the Lattice's JTAG-block. Can I just replace this with a generic JTAG TAP-controller, and then use a Xilinx-hosted Mico32 with a Lattice download-cable?


Lattice / M-LVDS

Started by Metin in comp.arch.fpga10 years ago 1 reply

Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LVDS? Are they true...

Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LVDS? Are they true M-LVDS driver/receivers? What are the deviations from the TIA/EIA-899 specification? Finally are They current-mode drivers? Thanks.


Re: new Lattice FPGAs vs Cyclone and SpartanIII

Started by Joseph H Allen in comp.arch.fpga13 years ago 2 replies

Have any of you tried Lattice's software for their new -EC parts? How close is it to Xilinx (they share a common heritage)? I'm trying to get a...

Have any of you tried Lattice's software for their new -EC parts? How close is it to Xilinx (they share a common heritage)? I'm trying to get a feel for its quality and stability. Things should be getting interesting when their 90nm -SC parts come out (vs. Stratix-II and Virtex-4), especially with their cool DDR I/O interface. Perhaps Lattice will make a come-back? -- /* jhallen@wo...


Lattice Announces EOL for XP and EC/P Product Lines

Started by rickman in comp.arch.fpga4 years ago 76 replies

This is likely not a big deal to most, but it hurts me a lot. I have one product in production and it uses an XP device. They are only...

This is likely not a big deal to most, but it hurts me a lot. I have one product in production and it uses an XP device. They are only giving until November to get your last time buy orders in. I think Lattice is doing a disservice to themselves as well as the rest of us. I am very accustomed to extended longevity in FPGAs. This act on the part of Lattice puts them in a separate camp...


Lattice Diamond 3.7 and Synplify

Started by rickman in comp.arch.fpga11 months ago 9 replies

I am trying to run the latest version of Lattice Diamond free edition. When I attempt to synthesize through the Diamond GUI I get "error code...

I am trying to run the latest version of Lattice Diamond free edition. When I attempt to synthesize through the Diamond GUI I get "error code 3". I've opened a ticket with Lattice support but after 2 weeks I am not getting anywhere with them. If there isn't something simple wrong with my project, they can't seem to be of much help and take two days to respond to every comment I make. ...


New Lattice FPGAs on 40nm ?

Started by Brane2 in comp.arch.fpga3 years ago 7 replies

I'm playing with Lattice's MachXO2 and ECP3 for a few months now and now that MachXO3 is about to come out I wonder what happened to ECP4. As I...

I'm playing with Lattice's MachXO2 and ECP3 for a few months now and now that MachXO3 is about to come out I wonder what happened to ECP4. As I understand it, Lattice found its market niche in low-power/low-cost branch, especially now when they bought BlueSilicon and incprporated their program in ice40 series. Knowing that they try to keep the cost down by using one process for all of their ...


Lattice "Open IP" license is GPL-compatible?

Started by Anonymous in comp.arch.fpga10 years ago 4 replies

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze...

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze or the lattice semi micro8. However, I'm worried about licensing issues, as I'd also like to be able to use the opencores IP and release the whole thing under the GPL. Does anyone know / have a strong opinion on whether or not the Lattice Open IP li...


Lattice pricing

Started by Richard Klingler in comp.arch.fpga10 years ago 1 reply

Good morning (o; Lattice Semiconductor has given up their website' (o; Anyway...I just wanted to ask what are the approx. prices for...

Good morning (o; Lattice Semiconductor has given up their website' (o; Anyway...I just wanted to ask what are the approx. prices for their new ECP2 devices in quantities up to 100? Strange that Lattice distributors don't have such a nice inventory and price/on-stock tool like EBV does (o; Also local distributor doesn't want to give out prices upfront of the ECP2 devices until he...


SERDES question (Lattice ispHSI)

Started by Przemyslaw Wegrzyn in comp.arch.fpga10 years ago 2 replies

Hi! I need to design a simple serializer/deserializer as part of my bigger experimental project. I've started with reading various application...

Hi! I need to design a simple serializer/deserializer as part of my bigger experimental project. I've started with reading various application notes from Lattice, Xilinx and Altera, as I don't feel very comfortable with multiple clock domain designs, nor with very high speed clocks in general. I've found one slightly confusing sketch in Lattice app. note, available here http://www.latti...


Lattice Breakout Boards

Started by Gabor in comp.arch.fpga6 years ago 6 replies

I often see people, especially hobbyists looking for inexpensive boards with a lot of non-dedicated I/O. These new boards from Lattice are...

I often see people, especially hobbyists looking for inexpensive boards with a lot of non-dedicated I/O. These new boards from Lattice are pretty basic (no on-board RAM) but have a lot of break-out pins for projects that just need a lot of I/O on 0.1" centers for prototyping. Usually Lattice releases boards like this at a "kicker" price and then quietly raises the price later, so you may ...


IC40HX PLL Simulation

Started by MK in comp.arch.fpga3 years ago

I'm trying to get started with a design using a Lattice ICE40HX (done that before) but this time I'm using the PLL. My usual design flow...

I'm trying to get started with a design using a Lattice ICE40HX (done that before) but this time I'm using the PLL. My usual design flow (with Lattice ECP3 or XP2) is to use the Lattice IP generator to make a VHDL entity which I drop into an Aldec HDL workspace where they happily compile and can be simulated. (works with PLLs, RAMs, DSP etc). The ICE40 tool makes two 'VHDL' files: (called p...


Lattice FPGA

Started by maxascent in comp.arch.fpga11 years ago 22 replies

Hi I was hoping to get some opinions on Lattice FPGAs compared to Xilinx and Altera. I see they have a SC device out. How does this compare to...

Hi I was hoping to get some opinions on Lattice FPGAs compared to Xilinx and Altera. I see they have a SC device out. How does this compare to similar devices from the other two? Cheers Jon


ISP interface

Started by David in comp.arch.fpga11 years ago 4 replies

Hi, I'm looking for some information on the proprietary ISP interface used by Lattice (specifically in the ispGDS22 device) I've managed to...

Hi, I'm looking for some information on the proprietary ISP interface used by Lattice (specifically in the ispGDS22 device) I've managed to find a Lattice document describing the function of the SDI,SDO,MODE + SCLK pins and the devices internal state machine, but nothing on specifically how to get the fuse map /JEDEC file into the device 'in-situ'. I've searched the Lattice website, but ...


Whups. Lattice Diamond says my package does not exist.

Started by Anonymous in comp.arch.fpga1 month ago 5 replies

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I...

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I is not available in the drop-down configuration menu. They say the closest they can get is the TQFP-100 or CSBGA-132 packages. My PCB and FPGA arrived days ago but I need a way to do development! Is there a way to configure Lattice Diamond


keep_hierarchy attribute equivalent for Lattice/Synplicity?

Started by theo...@gmail.com in comp.arch.fpga10 years ago 5 replies

I was wondering if anyone could help me figure out one thing that is holding us up for porting some Verilog code that works for Xilinx/ISE to...

I was wondering if anyone could help me figure out one thing that is holding us up for porting some Verilog code that works for Xilinx/ISE to Lattice/Synplicity. Specifically, for Xilinx, we use metacomments like this to prevent optimization across certain bits of logic: //synthesis attribute keep_hierarchy of mux0 is yes Would anyone happen to know the equivalent metacomment for Lattice...


Design tools comparison between Xilinx, Altera and Lattice for FPGA designs

Started by Luc in comp.arch.fpga12 years ago 7 replies

Guys, I'm trying to compare Altera, Xilinx and Lattice tools (free version) Can Xilinx, Altera and Lattice supporters comment? I...

Guys, I'm trying to compare Altera, Xilinx and Lattice tools (free version) Can Xilinx, Altera and Lattice supporters comment? I found: Lattice starter has included Leonardo/Precision RTL and Synplify, no ModelSim Xilinx ISE WebPack : XST, no Leonardo/Precision, no Synplify, no ModelSim Altera QuartusII Web Edition: support for Synplify, Precision and Modelsim? I know it's a simple c...


Lattice Semiconductor, Lattice Forums Go Live

Started by Anonymous in comp.arch.fpga11 years ago

Dear comp.arch.fpga'rs, Lattice Semiconductor went live with the company's first moderated support forum this week. We seeded the threads with...

Dear comp.arch.fpga'rs, Lattice Semiconductor went live with the company's first moderated support forum this week. We seeded the threads with our most popular FAQs and will continue to add to it over the new few weeks. I think you'll find some good content there already - so it's worth a look. Like other company sponsored forums registration is required to post and it will be moderated ...


EPLD Lattice Prog Problem

Started by max_mont in comp.arch.fpga11 years ago

Hi all, I'm developping an application on PowerPC to programm a Lattice EPLD. For that, I'm using ispVM Lattice player. When I programm the...

Hi all, I'm developping an application on PowerPC to programm a Lattice EPLD. For that, I'm using ispVM Lattice player. When I programm the CPLD which is already programmed by JTAG connector, all is running. But when I programm a new CPLD which has never been programmed, the programmation failed and I have message from VME player to tell that TDO signal is wrong. The CPLD is in a J...