Xilinx Virtex II MAC & PHY. ( HELP)

Started by Tony K in comp.arch.fpga13 years ago 2 replies

Hi I am working with Xilinx Virtex II FPGA. There is a soft core MAC and daughter card PHY. I am not using any kind of Stack. I am trying...

Hi I am working with Xilinx Virtex II FPGA. There is a soft core MAC and daughter card PHY. I am not using any kind of Stack. I am trying to implement Ethernet to Ethernet. I am able to send packet on the wire from the MAC through they PHY and I am able receive these packets back also through the PHY and MAC. I am able to do this loopback through writing bogus source MAC address and my o...


Virtex-4FX12MM: Any hardware MAC address accessable?

Started by Anonymous in comp.arch.fpga11 years ago 9 replies

Hi all, my hardware guys are on vacation but I need to clarify this: The EDK soft cores like opb_ethernetlite need the MAC address...

Hi all, my hardware guys are on vacation but I need to clarify this: The EDK soft cores like opb_ethernetlite need the MAC address as parameter. They do not provide a unique MAC address as default. You can imagine, what management effort would be necessary to maintain a unique MAC address for every device we deliver. Is there any MAC address available at the Virtex-4FX12MM that - is u...


fpga mac controller with tcp/ip/dhcp

Started by sundeep in comp.arch.fpga9 years ago 5 replies
MAC

hello, I am looking to create a mac controller which includes tcp/ip/dhcp. Where can I get information on how to do this? Within the mac...

hello, I am looking to create a mac controller which includes tcp/ip/dhcp. Where can I get information on how to do this? Within the mac controller I have started created a tx engine, rx engine, and flow controller. My mac controller will connect to an onboard phy chip, but I am unsure how to program the mac to interface with the phy for IEEE 802.11 standards. Such as, when a signal is ...


ethernet MAC and switch

Started by hema in comp.arch.fpga10 years ago 2 replies

Hello friends, I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC??? In switch controller...

Hello friends, I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC??? In switch controller implementation on FPGA does 4 tranceivers require 4 Ethernet MAC's???if so why??Because the source and the destination systems will have ethernet controller and MAC built in???please answer these questions.It's haunting me. Thanks. Regards, Hema.


XILINX POWERPC <-> Embedded tri-mode-MAC connection

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

Hi, I'm using the Xilinx Platform Studio and I'm tryng to connect the embedded tri-mode-MAC with the PowerPC405. reading the datasheet seems...

Hi, I'm using the Xilinx Platform Studio and I'm tryng to connect the embedded tri-mode-MAC with the PowerPC405. reading the datasheet seems that the PPC and the MAC are already connected to the DCR bus, but is not evident at all how to "see" in the XPS tree the MAC. I tryed to use the application "import/create user peripherial" without success. Does anyone have any experience at all? T...


ETHERNET MAC

Started by ashwin in comp.arch.fpga12 years ago 3 replies

Hello Everyone, I am doing a project on Implementing 10/100 ethernet mac on a fpga using vhdl. I saw the link on fpga4fun.com, its implemented...

Hello Everyone, I am doing a project on Implementing 10/100 ethernet mac on a fpga using vhdl. I saw the link on fpga4fun.com, its implemented in verilog and also i am not sure why he included ipaddreses and udp header. i guess mac addresses of PC and fpga board should be sufficient. I have many questions on this. Infact i would like to speak with or chat with anyone who know something ab...


advantages of ethernet MAC ip core

Started by Martin in comp.arch.fpga14 years ago 14 replies

Hi all! Can someone tell me the advantages and disadvantages of an ethernet MAC core implemented in a FPGA for a System On Chip? Why to buy...

Hi all! Can someone tell me the advantages and disadvantages of an ethernet MAC core implemented in a FPGA for a System On Chip? Why to buy a lincese for several thousand dollar for an ethernet MAC core and there is also an external PHY chip on the board? There are also external chips which combine the MAC and the PHY layer. Thanks Martin


EDK on Virtex4 FX using embedded ethernet MAC

Started by Pete in comp.arch.fpga12 years ago 4 replies

Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK offers several...

Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK offers several options for Ethernet MAC type but they are all soft MACs. The embedded MAC is a major selling point for me because of the logic saved and because compiling the soft MACs takes a long time. I will be connecting to a 10/100 switch using the MII port. Is...


ethernet phy or mac

Started by colin in comp.arch.fpga10 years ago 4 replies

Hi Does anyone have any experiences with connecting a MAC rather than a PHY to a spartan(3e). I don't know yet whether to use a microblaze...

Hi Does anyone have any experiences with connecting a MAC rather than a PHY to a spartan(3e). I don't know yet whether to use a microblaze or my own state machine to connect to the ethernet. For microblaze, xilinx cores seem to want just an external PHY but surely a MAC would offload more stuff from the FPGA. Any thoughts appreciated. Regards Colin


XilinX MAC FIR

Started by seb_tech_fr in comp.arch.fpga12 years ago 3 replies

Hi everybody, I'm working on a small project in which we want basically to filter Input data (Input Data Rate = 105Mhz) with a FIR filter...

Hi everybody, I'm working on a small project in which we want basically to filter Input data (Input Data Rate = 105Mhz) with a FIR filter (64 coefficients). I've forseen to use the MAC FIR IP provided by Xilinx but there could be a problem in the way input data are sampled. Indeed, MAC FIR IP provides an output named RFD(Ready For Data) which indicates when the MAC FIR can accept new data. Does ...


Does MAC FIR filter need special care?

Started by Sophi in comp.arch.fpga11 years ago 6 replies

Hi everyone, I am currently trying to implement a polyphase decimation filter by using core generator in ISE 7.1 The filter has been both...

Hi everyone, I am currently trying to implement a polyphase decimation filter by using core generator in ISE 7.1 The filter has been both implemented by using DA FIR and MAC. The DA FIR filter is working as it supposes to be, but MAC doesn't. I can't really see why. All the inputs and control signals feeding into these filters are the same. They are running in exactly the same environ...


Xilinx V4FX Embedded MAC.

Started by Marc Kelly in comp.arch.fpga11 years ago

Hi, I was wondering if someone who has used the embedded MAC's can give me a pointer here. I am using BaseX mode, with RocketIO to interface...

Hi, I was wondering if someone who has used the embedded MAC's can give me a pointer here. I am using BaseX mode, with RocketIO to interface to a a fibre SFP module then via fibre to a syskonnect card in a PC. I have finally got my rocketIO working, after a lot of messing around with all the settings and everything is working, or so it seems. However I am having trouble getting the MAC t...


floating point MAC, duh!

Started by Brannon in comp.arch.fpga11 years ago

[ranton] Considering the vast improvements in DSP-type IP and chip resources, I'm baffled as to why multiply-accumulate (MAC) is not included in...

[ranton] Considering the vast improvements in DSP-type IP and chip resources, I'm baffled as to why multiply-accumulate (MAC) is not included in the average set of floating point operator cores and FPUs. It just seems fundamental to me. Using heavily pipelined atomic multipliers and adders makes for an awefully slow MAC. [rantoff] Those wishing to impelement such a thing should look up Yong D...


Stupid question

Started by Thomas Womack in comp.arch.fpga12 years ago 13 replies

Is there any way of using the Xilinx toolchain on a Mac? I have become spoiled by my Mac Mini, and unpacking my loud PC just to run...

Is there any way of using the Xilinx toolchain on a Mac? I have become spoiled by my Mac Mini, and unpacking my loud PC just to run place-and-route seems inelegant. Tom


XILINX Ethernet MAC (URGENT...)

Started by vikram in comp.arch.fpga9 years ago 5 replies

hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i require Xilinx PLB Ethernet...

hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i require Xilinx PLB Ethernet MAC ip core. i must admit i am very new to such work, forgive my blatantness.... i would like to know: 1) What exactly do i get in the Xilinx Ethernet MAC ip core? (design files etc?) 2) Using XPS (EDK 9.1) and ISE 9.1, how do i integrate it int...


Replace MAC block with SGMII

Started by sundar in comp.arch.fpga8 years ago 1 reply
MAC

Hi All, I have a MII interface with 10/100 support in which MAC block is used as IP in my design. I am doing feasibility study of removinf...

Hi All, I have a MII interface with 10/100 support in which MAC block is used as IP in my design. I am doing feasibility study of removinf MAC block to external L2 component and use SGMII to support 10/100/1000. Is this possible? Also please let me know how are SerDes Channels listed in FPGA datasheets related to SGMII. Thanks, Sundar


Mutiple MAC on OPB Bus

Started by Venu in comp.arch.fpga10 years ago 3 replies

Hi, Is there any constraint regarding the number of Ethernet MAC that you can place on the OPB Bus? I have attempting to put 2 MACs on the...

Hi, Is there any constraint regarding the number of Ethernet MAC that you can place on the OPB Bus? I have attempting to put 2 MACs on the Bus, but as soon as a instantiate the second MAC and attempt to generate bitstream, I get the following error: address space overlap! This error is generated by PlatGen I am certain address overlap that this is not the problem , because I have gone t...


EMAC ping Board

Started by Mike_K in comp.arch.fpga13 years ago

Hi I am working with Virtex II EMAC and daughter care phy. I am able to send packet on the wire from the mac and receive these packet...

Hi I am working with Virtex II EMAC and daughter care phy. I am able to send packet on the wire from the mac and receive these packet back also. But If i ping (add an arp entry with MAC and IP) board I do not get these packets to come in. I am not using any kind of stack. I do get the packet onto the phy (atleast I think) but I don't generate any interrupt for the MAC. any ideas. thank...


FPGA MAC for Point to Point Connection

Started by Anonymous in comp.arch.fpga10 years ago

Hi everyone, I've been reading previous posts regarding ethernet MAC layers for FPGA's but can't seem to solve my problem. I'm going to be...

Hi everyone, I've been reading previous posts regarding ethernet MAC layers for FPGA's but can't seem to solve my problem. I'm going to be sending a receiving UDP packets from my PC to a PHY chip and then to my FPGA with a mac layer that I wrote in VHDL. It is a point to point connection and I can successfully receive packets when I set a static IP for the PC and broadcast. This projec...


How do i detect ethernet frames of layer 2 using ethereal?

Started by ashwin in comp.arch.fpga12 years ago 4 replies

Hello everyone, I am trying to implement ethernet MAC on a fpga using vhdl. I have a transmit module which generates the ethernet frame and...

Hello everyone, I am trying to implement ethernet MAC on a fpga using vhdl. I have a transmit module which generates the ethernet frame and transmits to the PC through the ethernet cable. The ethernet frame consists of preamble, sfd, destination(MAC), source(MAC), length,data,crc. I am using ethereal to detect this frame I definitely think that my crc is right. But i am not able to de...