Xilinx MIG fails

Started by Anonymous in comp.arch.fpga11 years ago 2 replies

I cannot get the MIG to work in Core Generator. I've written Xilinx, but hope I can get a faster answer here. I used the Tools-> Updates...

I cannot get the MIG to work in Core Generator. I've written Xilinx, but hope I can get a faster answer here. I used the Tools-> Updates Installer in coregen to install MIG. Help-> About now says I have IP updates 1 and MIG 1.6 installed. It also says I have MIG 1.5 installed. Xilinx says to list available cores by function, select Memories&Storage Elements, then select MIG. However MIG si


Anyone had success with MIG, DDR2 and V2Pro?

Started by Greg Watson in comp.arch.fpga11 years ago 3 replies

Hi We are planning to use MIG to generate a DDR2 interface for a V2Pro30 design, but I'd like to know if anyone has done this successfully...

Hi We are planning to use MIG to generate a DDR2 interface for a V2Pro30 design, but I'd like to know if anyone has done this successfully already? The MIG tool doesn't seem to have the quality level of other Xilinx tools and that makes me a bit nervous for something as timing critical as a DDR2 controller. We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So fa...


MIG for Linux?

Started by Duane Clark in comp.arch.fpga10 years ago 7 replies

So I thought I would try out this MIG thing I see mentioned occasionally, But according...

So I thought I would try out this MIG thing I see mentioned occasionally, But according to http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=25406 Software Requirements - ISE 9.2.01i - Windows XP (32 bit) So is MIG really windows only? I currently have ISE 8.2. That same page says: - MIG is no longer provided as a separate download, but is now incorpo...


Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface

Started by Berk in comp.arch.fpga7 years ago 9 replies

Hey everyone, I have been struggling to use the MIG to generate a memory interface to the DDR2 device. First some background info: I am using...

Hey everyone, I have been struggling to use the MIG to generate a memory interface to the DDR2 device. First some background info: I am using the Xilinx=AE Spartan=AE-3A DSP XtremeDSP=99 Starter Platform. I am using ISE 10.1 with MIG v2.3. I have created the MIG from GUI and played around with it. I also edited the UCF file (just changed the locations basically, did not mess around with...


Memory Interface Generator

Started by mlin in comp.arch.fpga8 years ago 4 replies

Hi, I am using MIG v2.1 that targets spartan 3 starter kit. I want to know, if sram on the starter board could be accessed using MIG and if the...

Hi, I am using MIG v2.1 that targets spartan 3 starter kit. I want to know, if sram on the starter board could be accessed using MIG and if the MIG is used for accessing memory development boards? Thanks in advance!


problem while adding externa MIG IP in design

Started by c4cheema in comp.arch.fpga7 years ago

Dear ALL I am facing this error time to time due to external IP Place:1240 - Placement has failed for the IP core generated by MIG because ...

Dear ALL I am facing this error time to time due to external IP Place:1240 - Placement has failed for the IP core generated by MIG because non-related components have been locked to slice locations required for the MIG core. Please change or remove the location constraints for these non-related components so that they don't conflict with MIG placement. Below is a list of the...


ddr2 sdram xilin mig controller, mig v1.72 issue

Started by Anonymous in comp.arch.fpga9 years ago

Hi, I am a design engineer, i have avnet xcv5lx110t board, it has a ddr2 sdram (mt47h14m16bg-5e, micron) attached, xilinx provides its...

Hi, I am a design engineer, i have avnet xcv5lx110t board, it has a ddr2 sdram (mt47h14m16bg-5e, micron) attached, xilinx provides its MIG controller, i installed mig v1.72 , and generated a ddr2 sdram controller, with data width 32, with its provided test bench. when i simulated the design with modelsim 6.1e, there were compiler errors that showed " data_dq runs out of its bounds", ...


MIG help (Virtex-6)

Started by spman in comp.arch.fpga5 years ago 1 reply

Hi I have created a controller for DDR3 with the MIG. The MIG output folders are example_design and user_design. according to MIG report : " ...

Hi I have created a controller for DDR3 with the MIG. The MIG output folders are example_design and user_design. according to MIG report : " - example_design: This folder includes the design with synthesizable test bench. - user_design: This folder includes the design without test bench modules. " But actually i don't see any important difference between these f...


Xilinx Mig bus functional model?

Started by Anonymous in comp.arch.fpga8 years ago

I'm starting to play with the Xilinx Mig for a DDR2 design. I have the basic logic generated by Mig simulating and the DDR2 model seems to...

I'm starting to play with the Xilinx Mig for a DDR2 design. I have the basic logic generated by Mig simulating and the DDR2 model seems to be twitching happily. Of course, it takes a while to simulate through the DDR2 setup and calibration. Does anyone have a bus function model of the user interface to the Mig DDR2 controller, ie, the app_* interface? I don't need/want to simulate t...


Basic Questions about MIG (Memory Interface Generator)

Started by Zorjak in comp.arch.fpga9 years ago 3 replies

Hi I need little help about ISE MIG tool. I have a couple baic questions and if someone can answer me I would be very greatfull. First thing...

Hi I need little help about ISE MIG tool. I have a couple baic questions and if someone can answer me I would be very greatfull. First thing I wanted to ask is: "does MIG gives me oportunity to define data bits aslo. I meant, in the UCF file that is generated at the end I can see only control signals. That is ok, yes? than in my design, I can define constraints about DATA ports as I want....


Xilinx MIG DDR2 initialization problems

Started by Anonymous in comp.arch.fpga10 years ago

I have used the MIG 1.72 tool to generate a memory interface for the DDR2 SODIMM on the Xilinx ML501 board. It works... sort of. I am using...

I have used the MIG 1.72 tool to generate a memory interface for the DDR2 SODIMM on the Xilinx ML501 board. It works... sort of. I am using the MIG synthesizable testbench as an indicator that the memory and controller are functioning correctly (which does some reads and writes to some addresses and makes sure they come back ok, otherwise asserts its 'error' output). The SIM_ONLY para...


Xilinx MIG 1.6 doesn't launch

Started by Your name in comp.arch.fpga11 years ago 6 replies

Hi there, I've recently installed the Xilinx ISE toolset so that I can play with the Memory Interface Generator. I followed the readme and...

Hi there, I've recently installed the Xilinx ISE toolset so that I can play with the Memory Interface Generator. I followed the readme and installed ISE 8.1i, 8.1i_SP3 and then MIG 1.6. When I open CORE Generator and select MIG from the drop down list nothing happens. I get the "Customise" and "View Data Sheet" links but when I click on them nothing happens. Is there another downlo...


MIG DDR2 controller does not work (reset problems?)

Started by Anonymous in comp.arch.fpga11 years ago 10 replies

Hi, I build a DDR2 controller using the Mig 1.5. In functional simulation everything works without problems (as alwayys). In the hardware...

Hi, I build a DDR2 controller using the Mig 1.5. In functional simulation everything works without problems (as alwayys). In the hardware implementation it does not work. I used the synthesizable testbench which is provided by the Mig. My design is driven by a 200Mhz Refclock and 125MHz system clock. I used chipscope and oscilloscope to figure out the following: -All clocks (200, 90, 50) ...


Where is MIG 1.7???

Started by GaLaKtIkUs™ in comp.arch.fpga10 years ago 3 replies

MIG 1.7 is already cited in the new versions of DDR2 SDRAM related application notes. There are also a few answer records about it. But there...

MIG 1.7 is already cited in the new versions of DDR2 SDRAM related application notes. There are also a few answer records about it. But there is no dowload link on Xilinx's site :(( Mehdi


Matching of the UCF files from MIG and ML403 turtoial demo

Started by agou in comp.arch.fpga11 years ago

Hi, I tried to use MIG to generate the DDR interface for FX12 on ML403 board. And the UCF generated by MIG is not consistent with the one...

Hi, I tried to use MIG to generate the DDR interface for FX12 on ML403 board. And the UCF generated by MIG is not consistent with the one from the ML403 tutorial demo. So I matched it by hand. The address and data bus are OK, but there are still some pins I don't know. Do you guys know their correspondence? Thanks. By the way, the DDR ram chip on ML403 is Infineon HYB25D256160BT-7, i....


Matching the UCF files from MIG and ML403 turtoial demo

Started by agou in comp.arch.fpga11 years ago

Hi, I tried to use MIG to generate the DDR interface for FX12 on ML403 board. And the UCF generated by MIG is not consistent with the one...

Hi, I tried to use MIG to generate the DDR interface for FX12 on ML403 board. And the UCF generated by MIG is not consistent with the one from the ML403 tutorial demo. So I matched it by hand. The address and data bus are OK, but there are still some pins I don't know. Do you guys know their correspondence? Thanks. By the way, the DDR ram chip on ML403 is Infineon HYB25D256160BT-...


Selective blocking of "-iobuf" directive in ISE

Started by wzab in comp.arch.fpga7 years ago

I'm integrating MIG generated core with big, formerly written and debugged design. The problem however is that the old design heavily relies on...

I'm integrating MIG generated core with big, formerly written and debugged design. The problem however is that the old design heavily relies on automatic generation of I/O buffers, while the MIG generated core requires the "-iobuf" option to be switched off. Is it possible to selectively switch off the automatic inferrence of the I/O buf for paticular signals (those provided by MIG generated...


Xilinx MIG

Started by Brad Smallridge in comp.arch.fpga11 years ago 2 replies

XAPP709 states that a 200-MHz DDR SDRAM can be built using MIG coregen, however, when I run mig006_rel6 ISE7.1.04, I don't see V4s on the drop...

XAPP709 states that a 200-MHz DDR SDRAM can be built using MIG coregen, however, when I run mig006_rel6 ISE7.1.04, I don't see V4s on the drop down selector. What's the story? Brad


ML402 DDR SDRAM

Started by Jered in comp.arch.fpga12 years ago 3 replies

Has anyone been able to get the ML402's DDR SDRAM running with a MIG-generated DDR controller, as opposed to the EDK PLB DDR controller? Xilinx...

Has anyone been able to get the ML402's DDR SDRAM running with a MIG-generated DDR controller, as opposed to the EDK PLB DDR controller? Xilinx is unable to confirm this works... there's a thread in this group from July with some ML401 MIG questions, but no resolution. My group is interested in using the 402 in a non-SoC application, so we're sort of wondering if MIG has been proven here. ...


MIG and Spartan3 for a 112 bit DQ bus (7chips x16)

Started by Dolphin in comp.arch.fpga9 years ago 1 reply

Hello, Has anybody tried to use MIG with a Spartan 3 to generate a memory controller that has a big DQ bus? I would like to generate a core...

Hello, Has anybody tried to use MIG with a Spartan 3 to generate a memory controller that has a big DQ bus? I would like to generate a core that controls 7 chips (x16), this results in 112 DQ pins. The chips would use a clock of 133MHz. Has anybody got experience with the MIG tool? Is it user-friendly or do you prefer to write your own DDR core? thanks and best regards, Karel