microsemi technical support

Started by alb in comp.arch.fpga4 years ago 4 replies

Hi everyone, this might be a stupid question to ask here but I really do not know where else I can post it. I filed 4 technical support...

Hi everyone, this might be a stupid question to ask here but I really do not know where else I can post it. I filed 4 technical support requests on the Microsemi website last Friday and, as of today, never had an answer back (not even a confirmation email of the request! [1]). They write on their page: > Your application request will be sent to Microsemi's team of > Application Support


Synplify Identify with Microsemi FPGAs

Started by ees3dc in comp.arch.fpga2 years ago 1 reply

Is anybody out there using Microsemi's Libero SoC and the bundled Synplfiy Identify? Identify is giving me problems: 1. It will not accept a...

Is anybody out there using Microsemi's Libero SoC and the bundled Synplfiy Identify? Identify is giving me problems: 1. It will not accept a depth of greater than 128 even when I ask for it 2. Gives completely wrong and impossible waveform results and gives the error message: ERROR: objectsdb_type.cpp:207: assertion '0' failed Since Synplify is bundled by Microsemi, I have no support w...


System On Chip From Microsemi

Started by rickman in comp.arch.fpga2 years ago 11 replies

I guess I stopped looking at the Microsemi products some time back. The SOC devices put out by Actel were ok, but the price was up there even...

I guess I stopped looking at the Microsemi products some time back. The SOC devices put out by Actel were ok, but the price was up there even for the smallest one, around $50. I was looking on Digikey and it seems their prices have come down and the new Smart Fusion 2 devices are even lower. The cheapest part is $16 qty at Digikey. These SOCs don't have any analog unless you consider...


Microsemi SmartFusion2 Field Upgrade

Started by Rob Gaddi in comp.arch.fpga3 months ago 4 replies

We're starting a new design, and I again find myself tempted by the Microsemi SmartFusion2 as combination FPGA/uC. It's got a built-in ARM...

We're starting a new design, and I again find myself tempted by the Microsemi SmartFusion2 as combination FPGA/uC. It's got a built-in ARM Cortex-M3, which is a simple dinky micro instead of some big honking A8 application processor that you can't even get up and running without kilobytes of boot code. The smallest, cheapest one is about $15 in small quantity with 64 kB of data memory ...


Microsemi FPGAs

Started by John Larkin in comp.arch.fpga3 months ago 3 replies

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or...

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or dislikes? They look like a pretty good deal for a medium FPGA with ARM. -- John Larkin Highland Technology, Inc lunatic fringe electronics


Signal Integrity Failure on Custom FPGA board

Started by elenappli in comp.arch.fpga3 years ago 3 replies

Hi I have just gotten a custom FPGA board in house and I am having trouble programming it. The FPGA I am using the Actel(Microsemi) Igloo...

Hi I have just gotten a custom FPGA board in house and I am having trouble programming it. The FPGA I am using the Actel(Microsemi) Igloo AGL250V2-FGG1441 There is a 10 pin JTAG header on the board. And I am using Microsemi's FlashPro3 to program it. The header of the FlashPro3 is 12 pins. There is a extra pin called VJTAGENB - that is used for IGLOO nano devices so I have left that pin uncon...


Actel bought by Microsemi

Started by HT-Lab in comp.arch.fpga7 years ago 16 replies

For those that haven't seen...

For those that haven't seen it: http://www.newelectronics.co.uk/article/28251/Actel-bought-by-analogue-specialist-in-430million- deal.aspx?u=71999 Hans www.ht-lab.com


RISC-V Support in FPGA

Started by rickman in comp.arch.fpga7 months ago 62 replies

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the...

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the link. https://www.microsemi.com/products/fpga-soc/technology-solutions/embedded-processing/risc-v -- Rick C


CoreABC from Microsemi

Started by alb in comp.arch.fpga4 years ago

Hi everyone, I'm currently laying down the architecture of an FPGA which is the main controller for a set of mechanisms and we wanted to...

Hi everyone, I'm currently laying down the architecture of an FPGA which is the main controller for a set of mechanisms and we wanted to profit of an amba ahb to interconnect various elements [1], included a slightly modified microblaze core (MB) with an additional floating point unit. The system does need to have an overall controller/sequencer or whatever you want to call it in ord...


Metastability mitigation and I/O registers

Started by RCIngham in comp.arch.fpga4 years ago 14 replies

This is a design targetted at a Microsemi ProASIC3 device, but I expect that the answer should be technology-independent. I have to input a...

This is a design targetted at a Microsemi ProASIC3 device, but I expect that the answer should be technology-independent. I have to input a bunch of discrete signals to send over a telemetry link. Therefore I will be doing the usual 2-register metastability mitigation. Should I pack the first register into the I/O cell, as per usual bus-related practice, or would it be better not to do that (...


MicroSemi Libero Software Installation Problems

Started by rickman in comp.arch.fpga1 year ago 7 replies

I have version 11.6 running on my laptop with Windows 8. For a workshop tomorrow I need to update to version 11.7 service pack 2. I downloaded...

I have version 11.6 running on my laptop with Windows 8. For a workshop tomorrow I need to update to version 11.7 service pack 2. I downloaded the software and started to install it, but I can't get past the initial directory creation. It actually makes the directory just fine, but the tool then complains this is not a valid directory. I've tried using different locations and changed...


looking for dev kit for ProAsic3

Started by alb in comp.arch.fpga3 years ago 7 replies

Hi everyone, I'm looking for a dev kit for a ProAsic3 A3PE3000 (microsemi) with some minimum amount of functional blocks around...

Hi everyone, I'm looking for a dev kit for a ProAsic3 A3PE3000 (microsemi) with some minimum amount of functional blocks around (volatile/non-volatile memory, few peripherals like UART, USB, SPI ...). So far I've found this interesting piece http://www.skylabs.si/DevBoard_PicoSky_a3pe3000.aspx but something simpler can work as well. The main reason is to use it as a testbed for ou...


Save money on (Xilinx,Altera,Microsemi,Lattice,Micron & More

Started by Stephen Flett in comp.arch.fpga4 years ago

Attention: If you buy electronic components and are looking to cut cost. I work with many OEM's & CM's helping them save money sourcing...

Attention: If you buy electronic components and are looking to cut cost. I work with many OEM's & CM's helping them save money sourcing for parts. (IC,SEMICONDUCTORS,FLASH,MEMORY,HARD DRIVES,LED,LCD,CONNECTORS ETC) If you have lead time issues or hard to find obsolete items you are looking for I can help you with that too! Please feel free to contact me for any component needs R...


Anybody got Microsemi/Actel Libero SoC 11.0 SP1 to work on linux?

Started by Svenn Are Bjerkem in comp.arch.fpga5 years ago 3 replies

Hi, Installation of 11.0Beta (the first complete download of Libero SoC 11.0) i= s ok and runs. When downloading and applying the SPA patch or...

Hi, Installation of 11.0Beta (the first complete download of Libero SoC 11.0) i= s ok and runs. When downloading and applying the SPA patch or SP1 patch, li= bero_bin exits with a missing symbol in a dynamic library. I note that in my installation a binary diff between the libero_bin of the = various patch levels does not indicate a change. There is, however, a chang= e in one of the dyn...


Save Money On (Xilinx,Micron,Altera,Lattice,Microsemi,Quick Logic & more

Started by Stephen Flett in comp.arch.fpga4 years ago

Attention: If you buy electronic components and are looking to cut cost. Please feel free to contact me. I work with many OEM's & CM's helping...

Attention: If you buy electronic components and are looking to cut cost. Please feel free to contact me. I work with many OEM's & CM's helping them save money sourcing for parts. If you have lead time issues or hard to find obsolete items you are looking for I can help you with that too! Please feel free to contact me for any component needs Regards, SFlett82@gmail.com


Why did Microsemi buy Actel?

Started by John Blyler in comp.arch.fpga7 years ago 5 replies

Three weeks ago, Intel announced the mid-year 2011 availability of the first programmable embedded ATOM SoC =96 codenamed Stellarton =96 based...

Three weeks ago, Intel announced the mid-year 2011 availability of the first programmable embedded ATOM SoC =96 codenamed Stellarton =96 based on Altera=92s FPGA technology. Earlier this year, Xilinx announced a partnership with ARM, the current de facto leader in embedded mobile systems. Both of these announcements were processor-centric, i.e., an embedded processor was tightly couple to an ...


New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment

Started by robotron in comp.arch.fpga5 years ago 25 replies

Dear colleagues, I am sending you a proposal of binary counter, designed to minimize logic path length in between flip-flops to one gate (MUX)...

Dear colleagues, I am sending you a proposal of binary counter, designed to minimize logic path length in between flip-flops to one gate (MUX) only, at the expense of not so straightforward binary counting. The reason for this design has emerged while using Actel (MicroSemi) ProASIC/IGLOO architecture, lacking any hardwired support for fast carry. I have placed VHDL code, schematics, tes...