Tcl used in Modelsim?

Started by Davy in comp.arch.fpga15 years ago 1 reply

Hi all, I am new to Modelsim and always use GUI to do all the work. I heard that we can use Tcl to control Modelsim to compile and run...

Hi all, I am new to Modelsim and always use GUI to do all the work. I heard that we can use Tcl to control Modelsim to compile and run a batch of work, is there any example available? BTW, I use Verilog. Any suggestions will be appreciated! Davy


Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)

Started by talkb in comp.arch.fpga13 years ago 17 replies

When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's Systemverilog...

When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's Systemverilog support was quite far behind Modelsim 6.2g. Now, I was wondering how these two products compare, today. Looking at Aldec's online manual, it seems Active-HDL 7.3 has caught up with Modelsim PE. (PE still supports some constructs that Aldec doesn't, but Alde...


Modelsim cannot run its example tcl

Started by fl in comp.arch.fpga10 years ago 2 replies

Hi, I want to learn tcl in Modelsim for FPGA simulation. I find that there is a directory under modelsim named tcl_tutorial\solutions. But...

Hi, I want to learn tcl in Modelsim for FPGA simulation. I find that there is a directory under modelsim named tcl_tutorial\solutions. But the traffic.do file cannot run with the following error message under dot line below. I have installed tcl/tk 8.6 on Windows XP. BTW, when I enter : help Tk It does give many Tk commands including winfo. What is wrong with my system? Thanks. Mod...


Problem with ModelSim and Xilinx PCIe endpoint block plus simulation

Started by Poojan Wagh in comp.arch.fpga12 years ago 2 replies

I'm trying to run through simulation of the PIO example given with Xilinx PCIe endpoint block plus. However, when I run modelsim with the .do...

I'm trying to run through simulation of the PIO example given with Xilinx PCIe endpoint block plus. However, when I run modelsim with the .do file given in the example, I get: vmap work {C:/Documents and Settings/PoojanW/My Documents/PCIeEPBP/ pciex4/simulation/functional/work} # Copying c:\modeltech_pe_6.5\win32pe/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Warning: Cop...


Modelsim XE III 6.x - huge fonts

Started by Dave Pollum in comp.arch.fpga13 years ago 5 replies

I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it displays everything in HUGE fonts. On my 21" monitor, each char is...

I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it displays everything in HUGE fonts. On my 21" monitor, each char is at least 1" tall. This happens whether I run Modelsim by itself, or when I run it from ISE Webpack 9.2.04i. I've downloaded the latest versions of both ISE Webpack and Modelsim XE from Xilinx's web site. I tried searching Xilinx's website but didn't find...


Modelsim error when doing: port map(a => not(b))

Started by JL in comp.arch.fpga15 years ago 1 reply

Hi all, I'm VERY sorry because I've seen much discussion about globally static expressions and Modelsim, but I cannot find a clear answer to...

Hi all, I'm VERY sorry because I've seen much discussion about globally static expressions and Modelsim, but I cannot find a clear answer to this problem. When you instantiate an entity, is quite common to negate one of the inputs. It would look something like this: i_my_entity : MyEntity port map( ena => not(nEN) ); When we pass it to Modelsim for pre-synthesis


Xilinx ISE : How to make Modelsim reload when design changed ?

Started by Mike Harrison in comp.arch.fpga16 years ago 2 replies

I've been experimenting with ISE Webpack, and have managed to create a simple schematic, and got the output waveforms in modelsim, however what...

I've been experimenting with ISE Webpack, and have managed to create a simple schematic, and got the output waveforms in modelsim, however what I can't figure out is how to get modelsim to reload the new data when I change the schematic - After I change the schematic and do 'create schematic symbol', the only way I can get it to simulate the new file is to close and re-launch modelsim - sur...


Modelsim problem

Started by in comp.arch.fpga15 years ago 5 replies

Hello, I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. However, if I use the "add wave *" command, ModelSim smply...

Hello, I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. However, if I use the "add wave *" command, ModelSim smply quits, regardless of what I put in the "*" field. Invoking it from FpgaAdvantage 6.1 shows me the following: Performing hierarchical generation through components... Checking which design units need saving Incrementally generating HDL... . . . Gene...


Modelsim simulation question

Started by Marco in comp.arch.fpga16 years ago

Hallo, I'm simulating a peripheral into modelsim. I have watched some differences between: behavioral, post-translate, post-map, post-place...

Hallo, I'm simulating a peripheral into modelsim. I have watched some differences between: behavioral, post-translate, post-map, post-place simulations. Using post-place simulation, the peripheral works well into modelsim. Instead, if I use post-map, modelsim shows some warnings like this: # Time: 299133929 ps Iteration: 7 Instance: /wave/uut/adc_ram_addr_write_0_1_399 # ** War...


Trouble with $readmemh in ModelSim

Started by Chris Carlen in comp.arch.fpga17 years ago 8 replies

Hi: I'm trying to use a memory in a Verilog testbench to generate arbitrary waveforms to stimulate my Verilog module. I'm using ModelSim...

Hi: I'm trying to use a memory in a Verilog testbench to generate arbitrary waveforms to stimulate my Verilog module. I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i. Modelsim complains with this message: # Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003 # -- Compiling module testbench # ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbe...


How to save preferences of modelsim

Started by fl in comp.arch.fpga15 years ago

Hi, The default font of the source window in Modelsim III 6.1e is too large. Although it is changed after I set it in "Tools-Edit Preferences",...

Hi, The default font of the source window in Modelsim III 6.1e is too large. Although it is changed after I set it in "Tools-Edit Preferences", it goes back the default value the next time I open Modelsim. How can I avoid this? Thank you very much.


ModelSim PE exit code 211

Started by Markus in comp.arch.fpga14 years ago 2 replies

When I try to run a timing simulation (simprim is used) modelsim pe student exits with fatal error and exit code 211. Modelsim XE works fine,...

When I try to run a timing simulation (simprim is used) modelsim pe student exits with fatal error and exit code 211. Modelsim XE works fine, but sloooow. Does anybody has some experience with this problem and an advice maybe?


Problem with Modelsim Lisence server...

Started by Debashish in comp.arch.fpga18 years ago 3 replies

Hi guys, Here i have a problem with my Modelsim lisence server.I have 2 lisences for modelsim in my office. But many a times if someone...

Hi guys, Here i have a problem with my Modelsim lisence server.I have 2 lisences for modelsim in my office. But many a times if someone dont close the modelsim properly or dont release the lisence (by command quit -sim), lisence stays active even if he is not working.So most of the time i am not able to use 2 linces. So being a Windows 2000 server we had to restart it again and agian atleast...


Modelsim: ROM initialisation

Started by Anonymous in comp.arch.fpga17 years ago 2 replies

I am using Modelsim XE II/Starter 5.7g to try and mdoel some ROM that I have instantiated using COREGEN. I have associated a .COE file with...

I am using Modelsim XE II/Starter 5.7g to try and mdoel some ROM that I have instantiated using COREGEN. I have associated a .COE file with the ROM in COREGEN with the values that I would like. However I get an error message in Modelsim when I try to run the simulation saying "failed to open VHDL file "romvalues.mif" in rb mode". Does anyone know how I can set up the init


Library Mapping

Started by ALuPin in comp.arch.fpga17 years ago

Hi, I want to perform a timing simulation in Modelsim. For that purpose it is necessary to do a library mapping for the Altera...

Hi, I want to perform a timing simulation in Modelsim. For that purpose it is necessary to do a library mapping for the Altera Cyclone library. In Modelsim (Altera 5.7e) there is a library called "Cyclone", I think it is a precompiled library. When reading the Altera Modelsim manual there is explained the following: "If using Model Technology's Modelsim, first create the device fa...


Will Modelsim XE 6.3c (Win32) run in Linux/WINE?

Started by arko in comp.arch.fpga13 years ago 5 replies

I've seen messages from regular posters saying that they run Modelsim/XE Starter Edition in Linux. This evidently works for the node-locked...

I've seen messages from regular posters saying that they run Modelsim/XE Starter Edition in Linux. This evidently works for the node-locked 'disk-id' based licenses. But if you have a full license, on a USB-dongle or other physical key, will Modelsim/XE still work under WINE?


Different Modelsim versions disagree in same backannotation!

Started by spectrallypure in comp.arch.fpga14 years ago 7 replies

Hi all! I am experiencing a very strange and rather frustrating problem while trying to run the same backannotated simulation in two...

Hi all! I am experiencing a very strange and rather frustrating problem while trying to run the same backannotated simulation in two different versions of Modelsim. In both cases I am using exactly the very same files for everything, and also the same compilation and simulation commands. The old version (Modelsim 5.8b) simulates fine and gives the expected results, while a newer release (Mode...


ModelSim is ungraceful with my stupidity...

Started by Gabor Szakacs in comp.arch.fpga17 years ago 2 replies

O.K. I did something stupid, but as a newbie to both Verilog and Modelsim I expected a nice error message instead of no indication and no...

O.K. I did something stupid, but as a newbie to both Verilog and Modelsim I expected a nice error message instead of no indication and no response while I watched all of my virtual memory get gobbled up. Then Modelsim closed (was killed by Windows). All because of: always PLX_LCLK0


Xilinx and Modelsim?

Started by Sunn in comp.arch.fpga13 years ago 5 replies

Hi, please forgive me for any ignorance in this question, but I am really lost. I have tried to get Xilinx ISE Webpack 9.2i to work with...

Hi, please forgive me for any ignorance in this question, but I am really lost. I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But it just doesn't seem to work. Now I am not very familiar with these programs, I am using them because I am doing a school course that uses FPGA and they use Xilinx and Modelsim... I have used them in the labs, but here I am just having tr...


ModelSim Xilinx edition new bug?

Started by Dan K in comp.arch.fpga14 years ago 2 replies

Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL...

Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL file and the Verilog file. When ModelSim sees the verilog file it grabs it and trys to use it but then errors out saying this version of ModelSim does not support a mixed design of both VHDL and Verilog. If I go in and delete the Verilog files eve...