ModelSim XE III error

Started by m.khairy in comp.arch.fpga11 years ago

Hi all i'm suing ISE 11.4 and ModelSim XE III when i do the behavioral simulation it works well but when i do the post place & route simulation...

Hi all i'm suing ISE 11.4 and ModelSim XE III when i do the behavioral simulation it works well but when i do the post place & route simulation the ModelSim report this errors "# ** Error: netgen/par/fpu_double_timesim.vhd(45842): (vcom-1141) Identifier "x_dsp48a1" does not identify a component declaration." how can i fix this error?! thanks in advance -------------------...


Re: Never buy Altera!!!!

Started by Matthew Hicks in comp.arch.fpga14 years ago 2 replies

You can use a TCL script in ModelSim to at least setup the simulation environment and wave window the way you want. Each time you want get the...

You can use a TCL script in ModelSim to at least setup the simulation environment and wave window the way you want. Each time you want get the setup just type do filename.do in ModelSim's command window. ModelSim is also good in that it gives you the the TCL command equivalent for most of the options you select and actions you take in the GUI (probably because that is how their kludgy ...


Modelsim on windoz save settings in a file rather than registry

Started by dgreig in comp.arch.fpga10 years ago 2 replies

Hi Is there any way of getting modelsim not to use the widoz registry for settings. I would prefer if it would use my .modelsim file. I...

Hi Is there any way of getting modelsim not to use the widoz registry for settings. I would prefer if it would use my .modelsim file. I find it impossible to express the extent of my disgust at having to temporally use such an abhorrent operating system for development!!!


Modelsim Error Code 211

Started by BrakePiston in comp.arch.fpga17 years ago 1 reply

Hi everybody, I am experiencing a weird problem with Modelsim 5.7d When i run my .do file with a "add wave" command, the program shuts....

Hi everybody, I am experiencing a weird problem with Modelsim 5.7d When i run my .do file with a "add wave" command, the program shuts. I have run it in command mode and I get that the error code is 211. Unfortunately, I have not found much about it on the modelsim website. Can anyone help? Thanks!


Modelsim Aliases

Started by Brad Smallridge in comp.arch.fpga16 years ago 3 replies

I would like to spilt up information on a memory data bus into its components. Some text have suggested aliases as a way of doing it. Is it the...

I would like to spilt up information on a memory data bus into its components. Some text have suggested aliases as a way of doing it. Is it the best way? Modelsim doesn't seem to show the aliases that I define, or, more likely, I don't know how to get Modelsim to show aliases. How is that done? Brad Smallridge b r a d @ a i v i s i o n . c o m 415-661-068


Simulating EDK 8.1i System using ModelSim 6.1e

Started by kits...@gmail.com in comp.arch.fpga15 years ago 6 replies

Hello, Recently, I have been trying to simulate my system to verify that the pieces are working correctly in my EDK project. In order to do...

Hello, Recently, I have been trying to simulate my system to verify that the pieces are working correctly in my EDK project. In order to do this, I need to use the SmartModel simulation tools for ModelSim 6.1e. I've read through all of Xilinx's documentation and have set up the modelsim.ini file correctly, but when I run the simulation, everything hangs. There are no calls to the BRAM t...


ModelSim versus Active-HDL....redux

Started by Anonymous in comp.arch.fpga13 years ago 9 replies

Hello all, I'm evaluating ModelSim versus Active-HDL to determine which one is better in today's marketplace (for VHDL). I found some older...

Hello all, I'm evaluating ModelSim versus Active-HDL to determine which one is better in today's marketplace (for VHDL). I found some older threads that seemed to lean towards Active-HDL so I wanted to see if that was still the case. I currently use ModelSim Xilinx Edition but my designs often-times hit XE's limits and get throttled. Also, does know off-hand the approximate price of ...


Xilinx edk/modelsim/ VHDL question

Started by MS in comp.arch.fpga17 years ago 2 replies

I am using the Xilinx EDK to perform simulations of the embedded PowerPC on a V2Pro. I have had success using simply the EDK with Modelsim but...

I am using the Xilinx EDK to perform simulations of the embedded PowerPC on a V2Pro. I have had success using simply the EDK with Modelsim but when I change the flow to the ISE as an embedded project- I am having trouble getting the boot ROM to be read in as a configuration in Modelsim. The trouble has to do with assigning the blockRAM configurations to the blockmemories once I wrapped th...


Content of RAM in Modelsim

Started by ALuPin in comp.arch.fpga17 years ago

Hi, I use the ALTSYNCRAM component in Altera QuartusII version 4.1 SP2 It has the following...

Hi, I use the ALTSYNCRAM component in Altera QuartusII version 4.1 SP2 It has the following ports: data_a[35..0] address_a[1..0] wren_a byteena_a[3..0] q_a[35..0] clock_a aclr_a data_b[35..0] address_b[1..0] wren_b q_b[35..0] clock_b aclr_b To make the content of the RAM visible during simulation with MODELSIM I choose the component ALTSYNCRAM in Modelsim and open the PR...


ModelSim & Constant

Started by Alexis GABIN in comp.arch.fpga16 years ago 2 replies

Hi, I want to know if it is possible to watch a constant in the Modelsim waveform viewer because I tried to make a model of ROM memory with...

Hi, I want to know if it is possible to watch a constant in the Modelsim waveform viewer because I tried to make a model of ROM memory with an array of std_logic_vector but when I adress the array it don't give me the right value (it seem to choose the first or the final one). So I would like to verify if Modelsim put the right value in the memory the declaration of the memory look lik...


Generating Modelsim Verilog resource libraries - pointers/questions

Started by Garrick in comp.arch.fpga16 years ago 6 replies

Hi, I have generated libraries in ModelSim 6.1 that my company is going to be distributing shortly. We need to protect our source code,...

Hi, I have generated libraries in ModelSim 6.1 that my company is going to be distributing shortly. We need to protect our source code, and I have a few concerns about the distribution. Currently, we plan on distributing the library in an installed directory, and the end users link this directory either at the command prompt or add it to the modelsim.ini file. Everything works gr...


Environmental variables to point at libraries with Modelsim?

Started by Nial Stewart in comp.arch.fpga12 years ago 4 replies

Hi all, In all my FPGA projects I try to keep everything uniform including directory structures for projects etc, this allowing the same...

Hi all, In all my FPGA projects I try to keep everything uniform including directory structures for projects etc, this allowing the same Modelsim VCOM command to be used throughout (ie compiling designs and testbanches to ../Modelsim/work). To stop having to compile the (usually) Altera libraries (altera_mf) into every project directory I usually have a 'central' library. Unfortunat...


Content of RAM

Started by ALuPin in comp.arch.fpga17 years ago

Hi, if I want to see the content of external SRAM in simulation (Modelsim) it is no problem because the memory of the VHDL SRAM model...

Hi, if I want to see the content of external SRAM in simulation (Modelsim) it is no problem because the memory of the VHDL SRAM model is represented by an variable field "memdata" which I can visualize in Modelsim. But how can I see the complete content of a RAM block (created with the MegaWizard in QuartusII) in Modelsim ? The only access to the memory are the ports wraddress, rdaddres...


Rocketio, modelsim xe

Started by ndt in comp.arch.fpga15 years ago 2 replies

Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to simulate it using modelsim XE. I know for the PE, SE version its using...

Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to simulate it using modelsim XE. I know for the PE, SE version its using smartmodels or generating libraries. Also is there any basic programs using rocketio, architect (wizard can't simulate, core generator can't compile libraries for modelsim, and the program that came with the eval board uses multiple buses, memory ...


ISE 9.1 and ModelSim XE III/Starter 6.2c: Distributed memory behaviorial simulation

Started by Udo in comp.arch.fpga14 years ago 1 reply

Hello, my design consits of a Softcore, a ROM and a RAM. For the RAM I'm using a Distributed Memory (v7.1) due to its size of only 256 * 8...

Hello, my design consits of a Softcore, a ROM and a RAM. For the RAM I'm using a Distributed Memory (v7.1) due to its size of only 256 * 8 bit. But I can't find that RAM in the ModelSim Workspace/Memories tabsheet. The ROM is there. Is the reason that the ROM is a block memory, that would mean a distributed memory isn't recognized as memory in ModelSim? Thanks for any hint Udo


How to make Altera-Modelsim free download version to work?

Started by Weng Tianxiang in comp.arch.fpga2 years ago 35 replies

Hi, I downloaded 11.0_modelsim_ase_windows.exe...

Hi, I downloaded 11.0_modelsim_ase_windows.exe from https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html Release Notes For ModelSim Altera 10.1b Apr 26 2012 Copyright 1991-2012 Mentor Graphics Corporation All rights reserved. After installing the software, I cannot run it:...


Xilinx 7.1 ISE ModelSim input files

Started by Brad Smallridge in comp.arch.fpga15 years ago 2 replies

I haven't been able to use my old testbenches with the new ISE simulator. I get an error saying that the input file was not generated by ISE. ...

I haven't been able to use my old testbenches with the new ISE simulator. I get an error saying that the input file was not generated by ISE. True, I used Paint to generate BMP files, and then I use to use ModelSim to simulate the results and output to another BMP file. I put in a case to Xilinx about this and the engineer told me how to switch the ISE simulation to ModelSim, but said t...


modelsim settings in edk

Started by Christoph Lauer in comp.arch.fpga15 years ago 2 replies

hi, I want to generate simulationlibrarys from edk 6.3 the wizard tells me I have to set the environment variable for modelsim. how do I do...

hi, I want to generate simulationlibrarys from edk 6.3 the wizard tells me I have to set the environment variable for modelsim. how do I do this in edk? thank you.


Checkpointing PPC Smartmodels in ModelSim 6.0b Issues

Started by Nju Njoroge in comp.arch.fpga15 years ago 4 replies

Hello, I have set-up checkpointing in ModelSim 6.0b (also using EDK 7.1 SP2). ModelSim complains that "two foreign architectures are missing...

Hello, I have set-up checkpointing in ModelSim 6.0b (also using EDK 7.1 SP2). ModelSim complains that "two foreign architectures are missing save and restore callbacks" when I checkpoint. These "foreign architectures" happen to be the PPC swift models. When I restore the checkpoints, the waveforms are fully restored. However, I cannot continue the simulation because it makes the following ...


Modelsim Warning

Started by FPGA in comp.arch.fpga13 years ago 5 replies

I am getting the following warning in Modelsim # ** Warning: Design size of 10053 statements or 1 leaf instances exceeds ModelSim PE Student...

I am getting the following warning in Modelsim # ** Warning: Design size of 10053 statements or 1 leaf instances exceeds ModelSim PE Student Edition recommended capacity. # Expect performance to be quite adversely affected. When I run simulations, I do not see any waveforms and it just freezes there forever. My design size if around 1000 lines. I do have other vhdl files for other projec...